illustris / FreeRTOS-RISCV

A port of FreeRTOS for the RISC-V ISA

OBSOLETE

This repository is no longer maintained, as RISC-V support was officially added to FreeRTOS.

• FreeRTOS homepage
• FreeRTOS ports
• Upstream repository
• Quickstart guide

FreeRTOS for RISC-V

This is a port of FreeRTOS to RISC-V

Contributors

The original port to priv spec 1.7 was contributed by Technolution

Update to priv spec 1.9: illustris

Update to priv spec 1.9.1: Abhinaya Agrawal

Bug fixes: Julio Gago

Update to priv spec 1.10: sherrbc1

Build

You can edit main() in main.c to add your FreeRTOS task definitions and set up the scheduler.

To build FreeRTOS,

cd Demo/riscv-spike
export RISCV=/opt/riscv # your riscv tools path here
make

Run

spike riscv-spike.elf

Tested environments

Tested on a Rocket RISC-V processor with local interrupt controller (Clint) using preemption.

Tested in Spike and Verilator with several builds including single-task, multi-task and typical demo test including queues, semaphores, mutexes and about a dozen concurrent tasks.