icerui11

Documentation

OSVVM Documentation

FmcPGA

A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for SUSTech EE332-Digital-System-Designing.

AMBA

AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog

rt-thread

RT-Thread is an open source IoT Real-Time Operating System (RTOS).

Asymmetric_async_FIFO

asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counter.

HDL_Converter

A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

AHB_SRAM

This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.

SpaceWireRouter

Fully functional SpaceWire router. Implemented in VHDL and under continuous development. See manual. Repository also contains a UART-SpaceWire adapter and several implementation files including constraints for Xilinx FPGAs.

SpaceWireToGigabitEther

Open-source version of SpaceWire-to-GigabitEther using ZestET1

debounce

A VHDL core to debounce an input

memory

Single Port RAM, Dual Port RAM, FIFO

Cache

Simple implementation of cache using VHDL

embox

Modular and configurable OS for embedded applications

core

SoCRocket - Core Repository

ccsds123

VHDL implementation of CCSDS123 compression standard

Libero_Sample_Project_With_Tcl_Script

Provided by Microchip support. This is a sample set of TCL scripts one can use to reconsittute a Libero project.

leon3-grlib-gpl-mirror

Automated Git mirror of Gaisler's GRLIB/Leon3 releases

Python2-Course

Python2.7教程

free-programming-books

:books: Freely available programming books

FPGADesignElements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

CustomizableComputingLab.github.io

FPGA_ThreeLevelStorage

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

harsh-payload

Harsh Environment CubeSat Payload designed to evaluate three different manufacturing nodes SDR SDRAM technologies under space radiation conditions. It was developed for the FloripaSat-2 CubeSat mission.

vhdl-experiments

All the mumbo jumbo code that is me learning VHDL. Primarily targeted for Microsemi Smartfusion2

SpaceWireCODECIP_100MHz

ccsds123

VHDL implementation of CCSDS123 compression standard

VHDL_Lib

Library of VHDL components that are useful in larger designs.

Backup-of-undergraduate-study-materials

本科学习资料备份

SoftConsole

Eclipse based IDE for RISC-V bare metal software development.

M2S150-Advanced-Dev-Kit

SmartFusion2 M2S150 Advanced Development Kit sample RISC-V Libero project(s)