hyperpicc

swerv-ISS

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

Modular-Exponentiation

Verilog Implementation of modular exponentiation using Montgomery multiplication

VerilogCodeECC

Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

gifenc

small C GIF encoder

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

sockit_spi

SocKit SPI (3-wire, dual, quad) master

sockit_owm

SocKit 1-wire (onewire) master

R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

light52

Yet another free 8051 FPGA core

Embedded-8051-based-Cryptosystem

An embedded 8051-based crypto system with a cryptographic coprocessor

light52

Lightweight 8051 compatible CPU

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

trng

True Random Number Generator core implemented in Verilog.

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

sha512

Verilog implementation of the SHA-512 hash function.

sha256

Hardware implementation of the SHA-256 cryptographic hash function

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

miaow

An open source GPU based off of the AMD Southern Islands ISA.

adv_jtag_bridge

adv_dbg_if

Universal Advanced JTAG Debug Interface

universal_jtag_tap

Universal JTAG TAP Controller

ahb3lite_interconnect

AHB3-Lite Interconnect

ahb3lite_apb_bridge

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

plic

Platform Level Interrupt Controller

RV12

RISC-V CPU Core

ahb3lite_memory

Multi-Technology RAM with AHB3Lite interface

gplgpu

GPL v3 2D/3D graphics engine in verilog