Harald Pretl (hpretl)

hpretl

Geek Repo

Company:Johannes Kepler University

Location:Linz, Austria

Home Page:https://iic.jku.at/analog/team/pretl

Twitter:@hpretl

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iic-jku

Harald Pretl's starred repositories

klayout

KLayout Main Sources

Language:C++License:GPL-3.0Stargazers:763Issues:0Issues:0

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

Language:CLicense:NOASSERTIONStargazers:104Issues:0Issues:0

magic

Magic VLSI Layout Tool

Language:CLicense:NOASSERTIONStargazers:462Issues:0Issues:0

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

Language:PythonLicense:Apache-2.0Stargazers:272Issues:0Issues:0

xschem

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

Language:CLicense:NOASSERTIONStargazers:304Issues:0Issues:0

OpenRAM

An open-source static random access memory (SRAM) compiler.

Language:PythonLicense:BSD-3-ClauseStargazers:803Issues:0Issues:0

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language:PythonLicense:Apache-2.0Stargazers:1288Issues:0Issues:0

python-deltasigma

A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep

Language:PythonLicense:NOASSERTIONStargazers:5Issues:0Issues:0

xschem_sky130

XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.

Language:VerilogLicense:Apache-2.0Stargazers:54Issues:0Issues:0