honeyxyb's repositories
Language:Verilog000
Some-useful-Perl-Scripts
These scrpits will be extremly useful in parsing Verilog files
Language:Perl000
riscv-libffi
RISC-V libffi port
Language:C000
scala_cookbook
Code for Alvin Alexander's book. Ebook ISBN:978-1-4493-4031-5
Language:Scala000
riscv-pythia
A RISC-V superscalar front-end simulator.
Language:Python000
xge_mac
Ethernet 10GE MAC
Language:Verilog000
xge_ll_mac
Ethernet 10GE Low Latency MAC
Language:Objective-C000
verilog_fixed_point_math_library
Fixed Point Math Library for Verilog
Language:VerilogLGPL-2.1000
systemverilog-uart16550
SystemVerilog uart16550
Language:SystemVerilog000
smii
Ethernet SMII
Language:Verilog000
robust_axi_fabric
Generic AXI interconnect fabric
Language:Verilog000
robust_axi2apb
Generic AXI to APB bridge
Language:Verilog000
robust_axi2ahb
Generic AXI to AHB bridge
Language:Verilog000
robust_ahb_matrix
Generic AHB matrix
Language:Verilog000
generic_fifos
Generic FIFOs
Language:Verilog000
ethmac10g
10G Ethernet MAC
Language:Verilog000
ethmac
Ethernet MAC 10/100 Mbps
Language:Verilog000
ethernet_tri_mode
10_100_1000 Mbps tri-mode ethernet MAC
Language:Verilog000
dma_axi
AXI DMA 32 / 64 bits
Language:Verilog000
dma_ahb
AHB DMA 32 / 64 bits
Language:Verilog000
ddr3_synthesizable_bfm
DDR3 Synthesizable BFM
Language:Verilog000
axi_slave
Generic AXI slave stub
Language:Verilog000
axi_master
Generic AXI master stub
Language:Verilog000
ahb_system_generator
ahb system generator
Language:VHDL000
ahb_slave
Generic AHB slave stub
Language:Verilog000
ahb_master
Generic AHB master stub
Language:Verilog000
ahb_arbiter
No description
Language:Verilog000
xsbt
*NOTE* sbt has moved to the sbt organization!
Language:ScalaNOASSERTION000