honeyxyb's repositories
axi-bfm
AXI3 Bus Functional Models (Master & Slave)
chisel-style-guide
A Style Guide for the Chisel Hardware Construction Language
chisel-template
A template project for beginning new Chisel work
chisel-testers
Provides various testers for chisel users
chisel-tutorial
chisel tutorial exercises and answers
chisel3
Chisel 3
chisel3-wiki
Mirror of Chisel3 Github wiki https://github.com/ucb-bar/chisel3/wiki
e200_opensource
The Ultra-Low Power RISC Core
Ethernet_switch_verification
Verification of Ethernet Switch System Verilog
ExaSwitch
ExaNest RTL switch with AXI-stream interface
IntelliJ-IDEA-Tutorial
IntelliJ IDEA 简体中文专题教程
my_cs_labs
My first chisel labs.
OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
riscv-4th-workshop-tutorials
4th RISC-V Workshop Tutorials
riscv-boom
Berkeley Out-of-Order Machine
riscv-boom-doc
Documentation for the BOOM processor
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC 6.1.0
riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
riscv_vhdl
VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
rocket-chip
Rocket Chip Generator
RV12
RISC-V CPU Core
sifive-blocks
Common RTL blocks used in SiFive's projects
translations
:panda_face: Chinese translations for classic IT resources
verilog-ethernet
Verilog Ethernet components
vscale
Verilog version of Z-scale
zscale
Z-scale Microarchitectural Implementation of RV32 ISA