hdlguy / gps_sim

An attempt to synthesize GPS signals in FPGA logic.

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gps_sim

An attempt to synthesize GPS signals in FPGA logic.

It is useful to have a GPS signal source that can be incorporated into FPGA logic to support receiver design. The idea is to have sufficient realism to test satellite acquisition and tracking. A realistic navigation solution is beyond the scope of this little project.

Goals:

  • Multiple satellite channels, perhaps 8.
  • C/A coarse acquisition sequence, selectable among the 37 possible.
  • Programmable noise source.
  • Signal strength adjustable per satellite
  • Doppler frequency shift adjustable per satellite
  • C/A code delay modelling

Stretch Goals:

  • P-Code sequence, modelled as an interferor.
  • 50 baud message data added to C/A sequence.

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An attempt to synthesize GPS signals in FPGA logic.

License:MIT License


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Language:Tcl 24.7%Language:Verilog 24.6%Language:C 23.2%Language:SystemVerilog 20.5%Language:MATLAB 5.2%Language:Makefile 1.3%Language:Stata 0.4%