hadirkhan10

caravel_ibtida_soc

MemCompose

chisel-noc-generator

This is a final project for CSE 228A "Agile Hardware Design" at UC Santa Cruz

caravan

A caravan equipped with API for creating bus protocols in Chisel with ease.

openlane-gui

A graphical user interface for the OpenLANE RTL-GDSII flow

picofoxy

Pipelined In-order Core for Artix-7 Arty-35T board

algorithms

bio

Buraq-mini

This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

chisel-circt

chisel-intermediate

CSE211-fa2022

Class website for CSE 211 at UCSC for the fall 2022 quarter

dotfile

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

firrtl

Flexible Intermediate Representation for RTL

gdb-stub

This is an implementation of a GDB stub later to be used inside Dromajo to give it the GDB support

hadirkhan10

hadirkhan10.github.io

hw1

HW1 for Agile Hardware Design

Ibtida-II

https://caravel-user-project.readthedocs.io

jigsaw

A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

sky130nm-inverter

Inverter layout designed in an open-source Skywater 130nm PDK

sky130nm-oscillator

A seven stage ring oscillator created by hand on the skywater-130nm open-source process design kit

sram-layout

test

TileLink

TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

tt05-leaky-neuron

A leaky integrate-and-fire neuron to be submitted in tinytapeout

workshops

exercises for workshops : https://www.gitbook.com/book/pawelwlodarski/workshops

Adv360-Pro-ZMK

Production repository for the all-new Advantage360 Professional using ZMK engine

snntorch

Deep and online learning with spiking neural networks in Python