germancq

lark

Lark is a parsing toolkit for Python, built with a focus on ergonomics, performance and modularity.

thonny

Python IDE for beginners

iverilog

Icarus Verilog

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

serv

SERV - The SErial RISC-V CPU

MySensors

MySensors library and examples

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

open-fpga-verilog-tutorial

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

MySensorsArduinoExamples

MySensors examples using external library dependencies

aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source

keywish-nano-plus

LCD_ST7032

Arduino library for ST7032 LCD controller with i2c interface

fusesoc-generators

A collection of core generators to use with FuseSoC

cocotbext-wishbone

logic-games

¿How to solve logic games using an FPGA? Let's do some experiments!

TerosHDLbackend

Backend for TerosHDL IDE