steveicarus / iverilog

Icarus Verilog

https://steveicarus.github.io/iverilog/

steveicarus/iverilog Issues

Possible Data Transfer Anomaly
Updated 25 days ago
I think a signal goes up one clock cycle too early
Updated a month ago1
vvp: array.cc:1561: void compile_array_alias(char*, char*, char*): Assertion `mem' failed.
Updated a month ago
Replication operator in literal array assignment pattern is not supported
Updated a month ago1
No error reported when an invalid or non-existent argument is passed to $bits
Updated a month ago
Array depth defined with the num method of an enum where the variable name is identical to part of the enum instance name causes an error
Closed a month ago5
vpi_put_value() at T0 is overridden
Closed a month ago2
OSSFuzz Integration
Updated a month ago12
Bug: accessing parameters by upward hierarchial name
Updated 2 months ago1
Support implicit named port connections
Closed 2 months ago5
Add support for `assert( l_c === 1'b0 );` syntax
Closed 2 months ago3
unsigned port connection sign extends
Closed 2 months ago4
iverilog doesn't exit with an error code when an include file is missing.
Closed 2 months ago4
fork..join_none inside automatic task fails assertion
Updated 2 months ago
Question on AMS support
Updated 3 months ago2
Feature request: add output coloring in terminals for keywords like "ERROR"
Updated 3 months ago7
Support for "inside" statements
Updated 3 months ago2
Override parameters in top-level Verilog
Closed 3 months ago2
Undetected error when a whole array is both procedurally and continuously assigned.
Closed 3 months ago1
Incorrect uninitialised value and force/release behaviour when variable is partly driven by a continuous assignment
Updated 3 months ago
Improve error message in module instantiation when `wire` array given to `output` array with wrong lengths
Updated 3 months ago
Net declarations using built-in types should be limited to 4-state data types
Closed 3 months ago5
The sv_literals test is not implemented
Closed 3 months ago5
The sv_parameter_type test hangs
Closed 3 months ago3
Arithmetics after a flip-flop causes wrong runtime value in specific circumstances
Closed 3 months ago2
The sv_interface test is not implemented
Closed 3 months ago2
array_packed_sysfunct test is not implemented
Updated 3 months ago
array/structure literals are not fully implemented
Updated 3 months ago2
array_packed_value_list test is not implemented
Closed 3 months ago2
The pr2509349a test has spurious output on Windows (msys2)
Closed 3 months ago
VPI: vpi_put_value() to a WIRE is not sticky.
Closed 4 months ago6
Performance issue for a simple generated design with XOR reductions
Closed 4 months ago8
Runtime error after a xor of concatenations after a latch
Closed 4 months ago2
The Iverilog compiler lacks a warning message for mismatched port widths after compilation.
Updated 4 months ago3
Iverilog hang on very large array of flops
Closed 4 months ago4
Assignments to enum with a ternary operator require explicit cast
Updated 4 months ago11
Iverilog not initializing the register with initial value
Updated 4 months ago4
Inability to use `local`/`protected` and `virtual` qualifiers simultaneously
Updated 4 months ago
cannot access package objects with vpi_handle_by_name()
Updated 4 months ago5
vpiFullName does not include :: for packages
Closed 4 months ago4
[Bug report] Segmentation fault when using out-of-scope variable in slices
Closed 4 months ago
Undeclared signal - but it works!
Closed 5 months ago4
github actions: The mingw32 run fails randomly
Closed 5 months ago
Where is the grammar parsing done?
Closed 5 months ago1
Implement DPI support
Updated 5 months ago
94879487
Closed 5 months ago
VPI: is vpi_handle_by_name() a good substitute for vpiLowConn?
Closed 6 months ago1
Accessing bit values of an enum inside a struct returns enum value instead of bit value
Closed 6 months ago2
$left / $right on packed structure field is `x` ?
Closed 6 months ago1
Arithmetic shift changes to logic shift after wait statement
Closed 6 months ago2