Ganesh Rahate's repositories
arrayfire
ArrayFire: a general purpose GPU library.
awesome-machine-learning
A curated list of awesome Machine Learning frameworks, libraries and software.
ModernSystemC
Example code for Modern SystemC using Modern C++
axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
bsg_manycore
Tile based architecture designed for computing efficiency, scalability and generality
C-Cpp-Notes
Notes about modern C++, C++11, C++14 and C++17, Boost Libraries, ABI, foreign function interface and reference cards.
common_cells
Common SV components
corundum
Open source, high performance, FPGA-based NIC
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
GPCore
This is the base repo for our graduation project in AlexU 21
gpgpu-sim_distribution
GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
modern-cpp-tutorial
📚 Modern C++ Tutorial: C++11/14/17/20 On the Fly
NyuziProcessor
GPGPU microprocessor architecture
openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
qemu
Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
verilog-axi
Verilog AXI components for FPGA implementation
warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
wb2axip
Bus bridges and other odds and ends