franciszekjuras / firIP

Implementation of FIR filter with time multiplexing and upsampling in Verilog.

finite-impulse-response fir verilog time-multiplexing upsampling dsp

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Implementation of FIR filter with time multiplexing and upsampling in Verilog.

finite-impulse-response fir verilog time-multiplexing upsampling dsp

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Language:Mathematica 85.8%Language:Verilog 10.2%Language:Tcl 3.2%Language:SystemVerilog 0.8%