Configuring Interrupts with Clint

[T. Platz]

I'm currently working on updating the BlackParrot core used with LiteX. I managed to get some output from the LiteX bios in the simulation, but the short pause in which I should be able to press Q or ESC to abort the boot process is always skipped.

Other cores, such as Vexriscv, introduce a small delay after printing

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.

In my case, however, the output directly continues with

sL5DdSMmkekro
Timeout
Executing booted program at 0x80000000
...

Further, pressing any key during the execution of the bios freezes the simulation, with no further output being printed. This made me think that my configuration of how interrupts are handled is not quite correct, yet. In my top module, I have a clint slice, which is connected to a Wishbone interface, but the traces show that no data every arrives via its interface.

My core.py configuration can be found here, but here is a summary of the parts I believe to be important:

io_regions = {
    0x5800_0000: 0x1800_0000
}

@property
def mem_map(self):
    return {
        "clint"    : 0x0030_0000,
        "csr"      : 0x5800_0000,
        "rom"      : 0x7000_0000,
        "sram"     : 0x7100_0000,
        "main_ram" : 0x8000_0000,
    }

def add_soc_components(self, soc):
    self.clintbus = clintbus = wishbone.Interface(data_width=64, adr_width=37, bursting=False)
    self.cpu_params.update(
        i_c00_adr_i = clintbus.adr,
        i_c00_dat_i = clintbus.dat_w,
        ...
        o_c00_dat_o = clintbus.dat_r,
    )
    soc.bus.add_slave("clint", clintbus, region=SoCRegion(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=True, linker=True))

For the code adding the clint slave, I mainly had a look at what the Rocket core and Naxriscv do, and adapted that according to BlackParrot's documentation. I have also tried declaring the clint region as not cached and adding an according IO region, but that did't work either. Is there anything obviously wrong about the config?

[T. Platz]

After some debugging, I found the root cause of the problem, which was not the clint configuration. Instead, the problem had something to do with the 32 bit internal WIshbone bus used by LiteX and the 64 bit interface used by BlackParrot, which caused some issues regarding alignment. As this was specific to the BlackParrot design, I will not go into more details about the exact problem.