Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler. Required programs for setting up the toolchain are flex, bison, gcc and make.
Compiler supports a limited subset of the C language (called Micro-C) and generates RV32I assembly code.
Run make in the riscv-toolchain/compiler directory.
./micro_riscv < example-file.mc
Simulator supports RV32I instruction set.
Run make in the riscv-toolchain/simulator directory.
Options are:
- -r Only print the result, without running the interactive mode
- -s Maximum number of instructions a simulator can execute
If no options are given, simulator will run in interactive mode for the maxmimum of 2000 instructions.
./riscvsim < sum_up_to.s
Disassembler supports RV64GC instruction sets and is made for testing wether the given program is compatible for execution on a Linux-compatible processor/microcontroller which supports given instruction sets.
Run make compile in the riscv-toolchain/disassembler directory.
Options are:
- -t X Architecture type, where X is 32/64/128
- -i Disassembles RVXI (base integer) instruction set
- -f Disassembles RVXF (single-precision, floating-point) standard extension
- -a Disassembles RVXA (atomic) standard extension
- -m Disassembles RVXM (multiplication) standard extension
- -d Disassembles RVXD (double-precision, floating-point, requires F standard extension) standard extension
- -c Disassembles RVXC (compressed) instruction set
- -e Disassembles RV32E (can only be combined with M,A,C standard extensions, used on embedded systems) instruction set
- -q Disassembles RV128Q (quad-precision, floating-point, requires RV64IFD instruction set) extension
- -h Show help
If no options are given the default instruction set is RV64GC (RV64IFAMDC)
./rv64dis examples/example4.bin
This program is free.
You can redistribute it and/or change it under the terms of GNU General Public License version 3.0 (GPLv3).
You can find the copy of the license in the repository.