dreamflyings's repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
aliyun-cli
Alibaba Cloud CLI
api-generator-sifive
Wake build descriptions of hardware generators
barstools
Useful utilities for BAR projects
block-pio-sifive
An example of on-boarding a PIO block in with duh and wake
busybox
BusyBox mirror
chisel-gui
A prototype GUI for chisel-development
chisel3
Chisel 3: A Modern Hardware Design Language
dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
dinocpu
A teaching-focused RISC-V CPU design used at UC Davis
dirv
This is my first trial project for designing RISC-V in Chisel
docs
TensorFlow documentation
environment-example-sifive
An example environment package
FireMarshal
Automatically Builds a Linux Distribution for FireSim/FireChip Nodes, works with FireSim's automatic workload generation.
freedom-metal
Bare Metal Compatibility Library for the Freedom Platform
gemmini-rocc-tests
Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
Greedy_Snake_Verilog
Greedy Snake game on Nexys 4 DDR with Verilog.
hammer
HAMMER: Highly Agile Masks Made Effortlessly from RTL
hosts
镜像：https://scaffrey.coding.net/p/hosts/git / https://git.qvq.network/googlehosts/hosts
lance-rocket
Rocket Chip Generatorや、Freedom SoCをベースとした、FPGA向けのRISC-V実装です
leeml-notes
李宏毅《机器学习》笔记，在线阅读地址：https://datawhalechina.github.io/leeml-notes
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-tools
RISC-V Tools (ISA Simulator and Tests)
RISCV-TOY
a very simple RISCV 5-stage CPU base chisel
verilog-pcie
Verilog PCI express components
yosys
Yosys Open SYnthesis Suite