dreamflyings's repositories
Ardon_SoC
Our SoC written in SpinalHDL.
chiselverify
A dynamic verification library for Chisel.
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
CSU-Thesis-LaTeX-Template
中南大学学位论文LaTeX模板
dingtalk
钉钉桌面版，基于electron和钉钉网页版开发，支持Windows、Linux和macOS
djl
An Engine-Agnostic Deep Learning Framework in Java
dma
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
edgeai-torchvision
Datasets, Transforms and Models specific to Computer Vision
F-CSP
Constraint Random Verification for Chisel3 and Chisel Tester2
flops-counter.pytorch
Flops counter for convolutional networks in pytorch framework
lastweek.github.io
Yizhou' Homepage
libgloss-htif
A libgloss replacement for RISC-V that supports HTIF
linux-on-litex-vexriscv
Linux on LiteX-VexRiscv
litex
Build your hardware, easily!
litex-vexriscv-tensorflow-lite-demo
TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board
math
SpinalHDL Hardware Math Library
ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
NutShell
RISC-V SoC designed by students in UCAS
openc910
OpenXuantie - OpenC910 Core
SaxonSoc
SoC based on VexRiscv and ICE40 UP5K
SpinalResNet
AdderNet ResNet20 for cifar10 written in SpinalHDL
SpinalTemplateSbtDependencies
An SpinalHDL project example which use VexRiscv git as a dependency
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
XiangShan
Open-source high-performance RISC-V processor
Xmind-
个人读书笔记