The Elements software development kit (SDK) is a hard-/software co-design tool to develop, debug and maintain all stacks of an open-source System on Chip (SoC).
It has various different projects included and supports choosing between open-source or vendor toolchains for FPGA and ASIC flow.
The full documentation is available at https://aesc-silicon.github.io/elements-sdk/.
- Open-Source FPGA flow
- Portfolio of configurable peripherals with OS support
- Predefined SOC platforms
- Integrated Operation Systems like Zephyr
- Toolchain files are generated automatically
- Nightly checks
Focus on defining a custom SOC and writing your application!
- Linux host system (Ubuntu 20.04 recommended)
- Python 3 (python3.8-dev)
- Vivado for Xilinx platforms (optional)
- Cadence for digital silicons (optional)
Install required packages:
sudo apt install ssh git curl libtool-bin autotools-dev automake pkg-config libyaml-dev sudo apt install libssl-dev gdb ninja-build flex bison libfl-dev sudo apt install python3 python3.8-dev python3-pip virtualenv openjdk-11-jdk-headless sudo apt install verilator gtkwave libcanberra-gtk-module libcanberra-gtk3-module sudo apt install libtinfo5 libncurses5
Download the repository and checkout the latest release:
git clone https://github.com/aesc-silicon/elements-sdk.git cd elements-sdk/ git checkout v22.1
Create a virtualenv:
virtualenv -p python3 venv
Install required packages for elements:
venv/bin/pip install pyyaml packaging
Initialise the SDK:
python3 elements.py init
The Vivado toolchain is not part of this SDK and needs to be installed separately for Xilinx
platforms from Xilinx's homepage. Download the Linux Self Extracting Web Installer for Version
2020.2 and install it. Select Vivado as product and Vivado HL WebPACK as Edition. You can use this
edition's license for free if you do not sell the bitstream, and disable everything except the
Artix-7 Platform to save disk storage. Elements except to find the Vivado toolchain under
/opt/xilinx.
chmod +x ~/Downloads/Xilinx_Unified_2020.2_1118_1232_Lin64.bin
~/Downloads/Xilinx_Unified_2020.2_1118_1232_Lin64.bin
The Elements SDK supports running inside Docker. Currently, only self-build images can be used due to a lack of uploading pre-build images.
A Docker Compose configuration is provided for systems that do not run with the recommended versions. The Docker will have included all required packages for the SDK, except vendor toolchains. Build the image (which can take some minutes).
docker-compose build
Next, start the Docker in the background.
docker-compose up -d
Afterward, all Python tools can be used identical to the CLI.
sudo docker exec -it elements_sdk_1 \
./elements-fpga.py Hydrogen1 Nexys4-DDR build zephyr-samples/demo/leds \
--toolchain symbiflow
Tip
Add --toolchain symbiflow as a parameter for the synthesize command to use the open-source
toolchain.
Finally, stop the Docker.
docker-compose stop
The docker image can also be used to develop. Therefore, the repos on the host system should be
forwarded to the container to make all changes public. Open the docker-compose.yml file and
uncomment the lines in volumes which should be made public.
Some GUI applications require access to the host system's X server. Run the following command in the host shell to grant them.
xhost local:root
| Board | Vendor | FPGA Chip |
|---|---|---|
| Nexys4-DDR | Digilent | Artix-7 |
| AX7101 | Alinx | Artix-7 |
| AX7035 | Alinx | Artix-7 |
| DH-006 | Phytec | Artix-7 |
| Foundary | PDK |
|---|---|
| IHP | SG13S |
| IHP | SG13S2 |
The complete documentation is hosted on https://aesc-silicon.github.io/elements-sdk/.
It describes the FPGA and ASIC flows and explains basic information and how to develop a simple Design.
The documentation can easily build with Sphinx. Therefore, run the Makefile inside the docsource folder.
source venv/bin/activate
make clean html -C docsource
firefox docsource/build/html/index.html
Copyright (c) 2022 aesc silicon. Released under the MIT license.