This repository contains the exam projects of the Architetture dei Sistemi Digitali course (AY 20/21) at the University of Naples Federico II.
The repository contains all the exercises developed in VHDL using Vivado 2022.1, which are described in the pdf documentation file. The examination projects are:
- Exercise1 : design, implementation and simulation of a 4:1 decoder, in structural and behavioural mode;
- Exercise2 : design, implementation and simulation of two sequence recognisers in different implementation modes;
- Exercise3 : design, implementation, simulation and synthesis on FPGA of a watch-chronometer;
- Exercise4 : design, implementation and simulation of a shift register with 4 operating modes;
- Exercise5 : design, implementation and simulation of a machine for calculating the modulus between two numbers;
- Exercise6 : design, implementation and simulation of a buffering comunication between two systems;
- Exercise7 : design, implementation and simulation of a component to calculate the scalar product between vectors;
- Exercise8 : study of MIC-1 processor operations and modification of an instruction;
- Exercise9 : design, implementation, simulation and synthesis on FPGA of two different modes of operation of the UART component;
- Exercise10 : design, implementation and simulation of a multi-stage switch using the omega-network model;
- Exercise11 : design, implementation, simulation and synthesis on FPGA of a Booth multiplier and a non-restoring divisor.