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csus-senior-design / ram_int_4p

4 port LPDDR2 memory interface for the Altera Cyclone 5 GX Starter Kit

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Please refer to the instructions in the source code file ram_int_4p.v for learning how to
instantiate and wire this module into the final top level design.

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4 port LPDDR2 memory interface for the Altera Cyclone 5 GX Starter Kit

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Language:Verilog 44.6%Language:SystemVerilog 32.2%Language:C 14.0%Language:Tcl 7.1%Language:C++ 1.0%Language:Shell 0.9%Language:HTML 0.1%Language:Forth 0.1%Language:VHDL 0.0%