CSUS CpE Senior Design - Team Honeybadger

Great-Horned-Owl

Head Tracking System

img_cap_top

The top level module for the stereoscopic image capture system on the Altera Cyclone 5 GX Starter Kit.

frame_buf_alt

Frame buffer implementation for the Altera Cyclone 5 GX starter board's LPDDR2 memory interface.

ram_int_4p

4 port LPDDR2 memory interface for the Altera Cyclone 5 GX Starter Kit

SeniorDesign-CAD-MODELS

CAD Models

DDR2Test

DDR Test

AtlysDDR2-Interface

cam_test

mem_test

A test for the LPDDR2 memory on the Altera Cyclone V GX Starter Kit.

display_pcb

Display PCB

LVDS_Implementation_v2.1

Need to update the pin and DCM_SP to DCM_CLK

ov_sccb

Omnivision SCCB Verilog Protocol Implementation

ov_7670

Verilog module for OV7670 CMOS Camera

videogen

img_cap_hdmi

camera_pcb

adv7513

frame_buf

Frame buffer for the camera data.

i2c

I2C Master and Slave

ram_int

Memory interface for the Altera UniPHY Hard Memory Controller on the Cyclone 5 GX FPGA.

hdmi

TMDS Encoder / Decoder

LVDS_Implementation

templates

Various templates to be used across projects

doc_problem_statement

Senior Design Documents