VHDL-synthesis using GHDL as option in addition to verific
tmeissner opened this issue · comments
I think it would be good to mention the possibility to use GHDL as plugin for Yosys as a second, open-source way to use VHDL as RTL language. Would be some additions in the RST and the toolchain-flow.svg image.
Maybe I could create a PR if there is interest.
@tmeissner - Most certainly be interested in seeing that, much of this was written before the GHDL plugin was viable...
Okay. I will create a PR when I've made the necessary additions to the docs.
Although GHDL is not available as a Conda package or supported in f4pga.flows yet, in #643 we added CI examples to show how to use a container along with the F4PGA Action in order to generate bitstreams for Xilinx's 7 Series devices from VHDL sources.