chipsalliance / UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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Reduce size of generated classes

hzeller opened this issue · comments

There is a lot of code that can be compacted by using the natural inheritance of the class hierachy. I've done a bunch last year, looks like it is a good time for another round.

commented

Could you add more information on what this task entails. Is this in context to chipsalliance/Surelog#1838?

An example would be #297.

Mostly the observation was that generated code was getting large in many cases there were switch-case statements generated in the code, but it was re-doing a lot of things for all the base-classes and then the object in question.
Also often with gigantic switch/case statements which will actually be a runtime issue (branches, non-local code etc.)

So the approach in the above mentioned pull request was to actually use the object hierachy, delegate some work to the super class and only do the remaining work in the final part.
I remember that there ware more things that can benefit from a likewise treatment.

commented

I intend to do similar treatment as in #297 to visitor and listener logic. I also intend to go a step further and reduce the logic in each implementation by calling its base class implementation.

void Base::DeepCopy(Base *const instance) const {
...
}

void Derived::DeepCopy(Derived *const instance) const {
    Base::DeepCopy(instance);
    ....
}

Derived* Derived::DeepClone() const {
    Derived *const instance = MakeInstance();
    DeepCopy(instance);
    return instance;
}

Sounds good. Making use of the class hierachy will bring a lot of gains.

commented

@hzeller #547 resolves this. If there is anything else that you think can be done, please report back.

This is all merged in.