Support a second parser (other than Surelog)
mithro opened this issue · comments
The goal of UHDM is to allow "users" (like Yosys, Verilator and Icarus) of a SystemVerilog parsers not to care about the exact parser implementation. However, currently the only parser which exposes the UHDM interface is Surelog.
Adding a second parser which also exposed the UHDM API would help verify that the API isn't over fitted to Surelog in any way.
I have a strong preference for that second parser to be Verible but I don't believe we have the development resources to do that work at the moment?
FYI - @hzeller
I started looking at this and had some questions about the model. Normally when using VPI the model is entirely the instantiated design, so each "module" is actually an instantiated instance with all parameter values set. When looking at, say, the genscope_cells example from the uhdm-integration repo, what I see is a bit confusing: there is an allModules array which has only one copy of the ibex_counter module even though there are two instances in the elaborated design. Is Surelog just picking one of the instances at random (probably the first occurrence) and throwing it into the "allModules" array? How does the tool decide which parts of an instance go in the "allModules" module and which go in the "vpiModule" entry within the genscope array? Are consumers expected to go back and re-elaborate the code in the allModules definition for each instance based on the actual param values?
Unrelated, but also wondering why all of the variables seem to be serialized as nets, with a vpiNetType of 36 which isn't one of the listed nettypes in the spec...
@alaindargelas ^ some questions for you
UHDM has a flat list of modules, interfaces, packages classes (Named allModules....) and the Elaborated list of topmodules called topModules with all their respective hierarchy elaborated.
The allModules is not used by any client applications yet as far as a know, although the concept of having an unelaborated view (modeling the unaltered lexical description of the modules) has it's use in linting, it is not the main goal and you can ignore it.
The topModules does contain all the elaboration users need and they do not need to perform extra elaboration task.
To be noted, in Surelog, the option -elabuhdm does not change the hierarchy structure (Even without this option, all generate statements are unrolled), but this option, or using the programmatic call to uhdm elaboration does uniquify the nets, functions and other objects that can be impacted by parameters.
To date the UHDM elaborated model does not reconcile lhs and rhs expression padding (And eventually that might get addressed), as both Verilator and Yosys backends do perform this operation.
Also the drivers/loads are not computed yet (A typical VPI implementation in a simulator does).
"Unrelated, but also wondering why all of the variables seem to be serialized as nets, with a vpiNetType of 36 which isn't one of the listed nettypes in the spec..."
The allModules view pays little attention to net types, the elaborated view sets all the right net types.
The instances in topModules does not seem to contain all of the information in the module though. For example, I don't seen any vpiProcesses and associated statements in there, or actually anything from the inside the module itself except for nested generate scopes. I'm using uhdm-dump on the output of the genscope_cells test by the way to inspect the database.
Also as far as I can tell the variables are serialized as nets in the topModules tree as well, it doesn't look any different to me.
I forgot, yes all the processes are not elaborated, so they reside in non-elaborated form in the allModules. Yosys and Verilator (The main targets for UHDM for now) do perform the final uniquification of the processes. The respective UHDM-Yosys UHDM-Verilator plugins do pass the elaborated tree from UHDM and the non-elaborated parts from the flat modules.
If you check examples like:
https://github.com/chipsalliance/Surelog/blob/master/tests/OneNet/OneNet.log
You should see some different types in the elaborated view.
Please open an Issue in Surelog with an example.
Ah, ok. Is there documentation of what gets elaborated and what does not? It's pretty confusing as-is. I see that continuous assigns don't show up in topModules, unless they're in a generate scope and then they do? Or is the model still a work in progress and not ready for another implementation?
I'll write up a complete description of the elaboration in the README
shortly.
Essentially, we are trying to keep the model as folded as possible, until
it really needs to be uniquified. The examples you give are an illustration
of that.
The allModules will contain the processes and assigns at the top module and
placeholder ports and nets.
The topModules will contain the hierarchy, the elaborated nets with the
correct type. the generate statements, the logic generated in the generate
statements...
The plugins for Verilator and Yosys do a bit of assembly. Making the model
fully elaborated, is actually quite trivial (clone everything all the
time), but the memory required is quite large and make the downstream
plugins have to explicitly translate every object to the native data
structures of Yosys and Verilator which in turn do some elaboration (memory
bloat).
Keeping the model folded saves on the plugin memory footprint, also des not
replicate what the client applications are doing in their internal
elaboration anyway.
But we could easily create an optional fully elaborated model (with all the
objects cloned from allModules to the topModules for regression purposes,
say to compare the UHDM generated model in between our 2 implementations.
…On Tue, Aug 17, 2021 at 9:23 AM Michael Popoloski ***@***.***> wrote:
Ah, ok. Is there documentation of what gets elaborated and what does not?
It's pretty confusing as-is. I see that continuous assigns don't show up in
topModules, unless they're in a generate scope and then they do? Or is the
model still a work in progress and not ready for another implementation?
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Thanks, that makes sense. Have you thought about alternative models that would more compactly represent the elaborated design? It seems like if you require all downstream consumers to reimplement all of the type checking and propagation logic it somewhat defeats the purpose of UHDM being the full frontend, as that logic is quite complicated. You say that it's simple but I don't see how it could be; changing the parameter values for a module can result in wildly different types involved in each expression of a process / continuous assign.
UHDM is a R/W model, so all the uniquification/type checking can be done
and annotated/substituted in the model itself by subsequent passes.
For Instance the -elabhm option of Surelog simply calls the UHDM Elaborator
class that clone UHDM objects (Say an assign stmt in a generate block and
bind the variables to the variables in the scope of the generate). That is
done by reading UHDM and writing back into UHDM. All the constant
propagation required to perform elaboration is done by Surelog, but
expressions that are "runtime" expressions are left unevaluated. One can
write an Evaluator on top of UHDM and decide to perform more evaluation
based on the UHDM model.
Similarly with the load/driver data, that can be computed from UHDM and
annotated back into UHDM.
All of these middle layer applications are in the TODO list.
To date I see 2 types of customer for UHDM,
- the Yosys/Verilator applications that already perform the additional
tasks above (So not an emergency for them),
- The lighter weight applications like State machine analyzer, netlist
viewer, linters that would benefit from these extra services but who
already make good use of the folded model.
…On Tue, Aug 17, 2021 at 1:39 PM Michael Popoloski ***@***.***> wrote:
Thanks, that makes sense. Have you thought about alternative models that
would more compactly represent the elaborated design? It seems like if you
require all downstream consumers to reimplement all of the type checking
and propagation logic it somewhat defeats the purpose of UHDM being the
full frontend, as that logic is quite complicated. You say that it's simple
but I don't see how it could be; changing the parameter values for a module
can result in wildly different types involved in each expression of a
process / continuous assign.
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@MikePopoloski, coming back to this after a while, sorry...
I changed the README to have more explanations.
I also realized the the Antmicro team is not using the -elabuhdm Surelog option which does bloat the memory, but also does what you are looking for.
That option (modulo bugs I'd be happy to fix) does indeed clone all objects including processes.
So on the example you are pointing out,
https://github.com/chipsalliance/UHDM-integration-tests/blob/master/tests/genscope_cells/dut.sv
surelog -parse -elabuhdm -d uhdm -d vpi_ids
Produces the following fully elaborated tree (including processes and assigns):
....
|uhdmtopModules:
\_module: work@dut (work@dut), id:444 tests/ScratchPad.sv:30:1: , endln:55:10
|vpiDefName:work@dut
|vpiName:work@dut
|vpiGenScopeArray:
\_gen_scope_array: (work@dut.gen_modules[0]), id:465, line:41:41, endln:51:4, parent:work@dut, parID:444
|vpiName:gen_modules[0]
|vpiFullName:work@dut.gen_modules[0]
|vpiGenScope:
\_gen_scope: (work@dut.gen_modules[0]), id:466, parent:work@dut.gen_modules[0], parID:465
|vpiFullName:work@dut.gen_modules[0]
|vpiModule:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiDefName:work@ibex_counter
|vpiDefFile:tests/ScratchPad.sv
|vpiDefLineNo:57
|vpiName:module_in_genscope
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiPort:
\_port: (clk_i), id:676, line:60:23, endln:60:28, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:clk_i
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (work@dut.gen_modules[0].clk), id:677, line:43:42, endln:43:45, parent:clk_i, parID:676
|vpiName:clk
|vpiFullName:work@dut.gen_modules[0].clk
|vpiActual:
\_logic_net: (work@dut.clk), id:128, line:34:7, endln:34:10, parent:work@dut, parID:444
|vpiName:clk
|vpiFullName:work@dut.clk
|vpiNetType:36
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.clk_i), id:678, parent:clk_i, parID:676
|vpiName:clk_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.clk_i
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.clk_i), id:513, line:60:23, endln:60:28, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:clk_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.clk_i
|vpiNetType:36
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiPort:
\_port: (rst_ni), id:679, line:61:23, endln:61:29, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:rst_ni
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (work@dut.gen_modules[0].rst), id:680, line:44:43, endln:44:46, parent:rst_ni, parID:679
|vpiName:rst
|vpiFullName:work@dut.gen_modules[0].rst
|vpiActual:
\_logic_net: (work@dut.rst), id:129, line:35:7, endln:35:10, parent:work@dut, parID:444
|vpiName:rst
|vpiFullName:work@dut.rst
|vpiNetType:36
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.rst_ni), id:681, parent:rst_ni, parID:679
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.rst_ni
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.rst_ni), id:514, line:61:23, endln:61:29, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.rst_ni
|vpiNetType:36
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiPort:
\_port: (counter_inc_i), id:682, line:63:23, endln:63:36, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_inc_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counter_inc_i), id:683, line:45:50, endln:45:66, parent:counter_inc_i, parID:684
|vpiName:counter_inc_i
|vpiFullName:work@dut.counter_inc_i
|vpiIndex:
\_ref_obj: (counter_inc_i.i), id:685, line:45:64, endln:45:65, parent:work@dut.counter_inc_i, parID:683
|vpiName:i
|vpiFullName:counter_inc_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[0].i), id:451, line:41, parent:work@dut.gen_modules[0], parID:466
|vpiName:i
|vpiFullName:work@dut.gen_modules[0].i
|UINT:0
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_inc_i), id:686, parent:counter_inc_i, parID:682
|vpiName:counter_inc_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_inc_i
|vpiActual:
\_logic_net: (work@dut.counter_inc_i), id:136, line:36:24, endln:36:37, parent:work@dut, parID:444
|vpiName:counter_inc_i
|vpiFullName:work@dut.counter_inc_i
|vpiNetType:36
|vpiRange:
\_range: , id:130, line:36:8, endln:36:23
|vpiLeftRange:
\_constant: , id:134, line:36:8, endln:36:19, parID:130
|vpiConstType:7
|vpiDecompile:1
|vpiSize:64
|INT:1
|vpiRightRange:
\_constant: , id:135, line:36:22, endln:36:23, parID:130
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiPort:
\_port: (counterh_we_i), id:687, line:64:23, endln:64:36, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counterh_we_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counterh_we_i), id:688, line:46:50, endln:46:66, parent:counterh_we_i, parID:689
|vpiName:counterh_we_i
|vpiFullName:work@dut.counterh_we_i
|vpiIndex:
\_ref_obj: (counterh_we_i.i), id:690, line:46:64, endln:46:65, parent:work@dut.counterh_we_i, parID:688
|vpiName:i
|vpiFullName:counterh_we_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[0].i), id:451, line:41, parent:work@dut.gen_modules[0], parID:466
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counterh_we_i), id:691, parent:counterh_we_i, parID:687
|vpiName:counterh_we_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counterh_we_i
|vpiActual:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiName:counterh_we_i
|vpiFullName:work@dut.counterh_we_i
|vpiNetType:36
|vpiRange:
\_range: , id:137, line:37:8, endln:37:23
|vpiLeftRange:
\_constant: , id:141, line:37:8, endln:37:19, parID:137
|vpiConstType:7
|vpiDecompile:1
|vpiSize:64
|INT:1
|vpiRightRange:
\_constant: , id:142, line:37:22, endln:37:23, parID:137
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiPort:
\_port: (counter_we_i), id:692, line:65:23, endln:65:35, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_we_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counter_we_i), id:693, line:47:49, endln:47:64, parent:counter_we_i, parID:694
|vpiName:counter_we_i
|vpiFullName:work@dut.counter_we_i
|vpiIndex:
\_ref_obj: (counter_we_i.i), id:695, line:47:62, endln:47:63, parent:work@dut.counter_we_i, parID:693
|vpiName:i
|vpiFullName:counter_we_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[0].i), id:451, line:41, parent:work@dut.gen_modules[0], parID:466
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_we_i), id:696, parent:counter_we_i, parID:692
|vpiName:counter_we_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_we_i
|vpiActual:
\_logic_net: (work@dut.counter_we_i), id:150, line:38:24, endln:38:36, parent:work@dut, parID:444
|vpiName:counter_we_i
|vpiFullName:work@dut.counter_we_i
|vpiNetType:36
|vpiRange:
\_range: , id:144, line:38:8, endln:38:23
|vpiLeftRange:
\_constant: , id:148, line:38:8, endln:38:19, parID:144
|vpiConstType:7
|vpiDecompile:1
|vpiSize:64
|INT:1
|vpiRightRange:
\_constant: , id:149, line:38:22, endln:38:23, parID:144
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiPort:
\_port: (counter_val_i), id:697, line:66:23, endln:66:36, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_val_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counter_val_i), id:698, line:48:50, endln:48:66, parent:counter_val_i, parID:699
|vpiName:counter_val_i
|vpiFullName:work@dut.counter_val_i
|vpiIndex:
\_ref_obj: (counter_val_i.i), id:700, line:48:64, endln:48:65, parent:work@dut.counter_val_i, parID:698
|vpiName:i
|vpiFullName:counter_val_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[0].i), id:451, line:41, parent:work@dut.gen_modules[0], parID:466
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_val_i), id:701, parent:counter_val_i, parID:697
|vpiName:counter_val_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_val_i
|vpiActual:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiName:counter_val_i
|vpiFullName:work@dut.counter_val_i
|vpiNetType:36
|vpiRange:
\_range: , id:151, line:39:8, endln:39:23
|vpiLeftRange:
\_constant: , id:155, line:39:8, endln:39:19, parID:151
|vpiConstType:7
|vpiDecompile:1
|vpiSize:64
|INT:1
|vpiRightRange:
\_constant: , id:156, line:39:22, endln:39:23, parID:151
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiRange:
\_range: , id:157, line:39:25, endln:39:29
|vpiLeftRange:
\_constant: , id:158, line:39:25, endln:39:27, parID:157
|vpiConstType:9
|vpiDecompile:31
|vpiSize:64
|UINT:31
|vpiRightRange:
\_constant: , id:159, line:39:28, endln:39:29, parID:157
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiPort:
\_port: (counter_val_o), id:702, line:67:23, endln:67:36, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_val_o
|vpiDirection:2
|vpiHighConn:
\_bit_select: (work@dut.counter_val_o), id:703, line:49:50, endln:49:66, parent:counter_val_o, parID:704
|vpiName:counter_val_o
|vpiFullName:work@dut.counter_val_o
|vpiIndex:
\_ref_obj: (counter_val_o.i), id:705, line:49:64, endln:49:65, parent:work@dut.counter_val_o, parID:703
|vpiName:i
|vpiFullName:counter_val_o.i
|vpiActual:
\_parameter: (work@dut.gen_modules[0].i), id:451, line:41, parent:work@dut.gen_modules[0], parID:466
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_val_o), id:706, parent:counter_val_o, parID:702
|vpiName:counter_val_o
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_val_o
|vpiActual:
\_logic_net: (work@dut.counter_val_o), id:170, line:40:31, endln:40:44, parent:work@dut, parID:444
|vpiName:counter_val_o
|vpiFullName:work@dut.counter_val_o
|vpiNetType:36
|vpiRange:
\_range: , id:161, line:40:8, endln:40:23
|vpiLeftRange:
\_constant: , id:165, line:40:8, endln:40:19, parID:161
|vpiConstType:7
|vpiDecompile:1
|vpiSize:64
|INT:1
|vpiRightRange:
\_constant: , id:166, line:40:22, endln:40:23, parID:161
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiRange:
\_range: , id:167, line:40:25, endln:40:29
|vpiLeftRange:
\_constant: , id:168, line:40:25, endln:40:27, parID:167
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:169, line:40:28, endln:40:29, parID:167
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[0].module_in_genscope), id:467 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[0], parID:466
|vpiProcess:
\_always: , id:593, line:77:3, endln:99:6, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiAlwaysType:2
|vpiStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:594, line:77:15, endln:99:6, parID:593
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_assignment: , id:595, line:80:5, endln:80:38, parent:work@dut.gen_modules[0].module_in_genscope, parID:594
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_operation: , id:597, line:80:10, endln:80:22, parID:595
|vpiOpType:29
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_we_i), id:598, line:80:10, endln:80:22, parID:597
|vpiName:counter_we_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_we_i
|vpiActual:
\_logic_net: (work@dut.counter_we_i), id:150, line:38:24, endln:38:36, parent:work@dut, parID:444
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counterh_we_i), id:599, line:80:25, endln:80:38, parID:597
|vpiName:counterh_we_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counterh_we_i
|vpiActual:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.we), id:596, line:80:5, endln:80:7, parID:595
|vpiName:we
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.we
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.we), id:521, line:73:28, endln:73:30, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:we
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.we
|vpiNetType:36
|vpiStmt:
\_assignment: , id:600, line:81:5, endln:81:41, parent:work@dut.gen_modules[0].module_in_genscope, parID:594
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:603, line:81:27, endln:81:41, parent:work@ibex_counter.counter, parID:604
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:604, parent:work@ibex_counter.counter, parID:26
|vpiLeftRange:
\_constant: , id:23, line:81:35, endln:81:37
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:24, line:81:38, endln:81:40
|vpiConstType:9
|vpiDecompile:32
|vpiSize:64
|UINT:32
|vpiLhs:
\_part_select: , id:601, line:81:5, endln:81:17, parent:work@ibex_counter.counter_load, parID:602
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:602, parent:work@ibex_counter.counter_load, parID:22
|vpiLeftRange:
\_constant: , id:19, line:81:18, endln:81:20
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:20, line:81:21, endln:81:23
|vpiConstType:9
|vpiDecompile:32
|vpiSize:64
|UINT:32
|vpiStmt:
\_assignment: , id:605, line:82:5, endln:82:40, parent:work@dut.gen_modules[0].module_in_genscope, parID:594
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_val_i), id:608, line:82:27, endln:82:40, parID:605
|vpiName:counter_val_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_val_i
|vpiActual:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiLhs:
\_part_select: , id:606, line:82:5, endln:82:17, parent:work@ibex_counter.counter_load, parID:607
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:607, parent:work@ibex_counter.counter_load, parID:31
|vpiLeftRange:
\_constant: , id:28, line:82:18, endln:82:20
|vpiConstType:9
|vpiDecompile:31
|vpiSize:64
|UINT:31
|vpiRightRange:
\_constant: , id:29, line:82:21, endln:82:22
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiStmt:
\_if_stmt: , id:609, line:83:5, endln:86:8, parent:work@dut.gen_modules[0].module_in_genscope, parID:594
|vpiCondition:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counterh_we_i), id:610, line:83:9, endln:83:22, parID:609
|vpiName:counterh_we_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counterh_we_i
|vpiActual:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:611, line:83:24, endln:86:8, parID:609
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_assignment: , id:612, line:84:7, endln:84:42, parent:work@dut.gen_modules[0].module_in_genscope, parID:611
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_val_i), id:615, line:84:29, endln:84:42, parID:612
|vpiName:counter_val_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_val_i
|vpiActual:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiLhs:
\_part_select: , id:613, line:84:7, endln:84:19, parent:work@ibex_counter.counter_load, parID:614
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:614, parent:work@ibex_counter.counter_load, parID:40
|vpiLeftRange:
\_constant: , id:37, line:84:20, endln:84:22
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:38, line:84:23, endln:84:25
|vpiConstType:9
|vpiDecompile:32
|vpiSize:64
|UINT:32
|vpiStmt:
\_assignment: , id:616, line:85:7, endln:85:42, parent:work@dut.gen_modules[0].module_in_genscope, parID:611
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:619, line:85:29, endln:85:42, parent:work@ibex_counter.counter, parID:620
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:620, parent:work@ibex_counter.counter, parID:50
|vpiLeftRange:
\_constant: , id:47, line:85:37, endln:85:39
|vpiConstType:9
|vpiDecompile:31
|vpiSize:64
|UINT:31
|vpiRightRange:
\_constant: , id:48, line:85:40, endln:85:41
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiLhs:
\_part_select: , id:617, line:85:7, endln:85:19, parent:work@ibex_counter.counter_load, parID:618
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:618, parent:work@ibex_counter.counter_load, parID:46
|vpiLeftRange:
\_constant: , id:43, line:85:20, endln:85:22
|vpiConstType:9
|vpiDecompile:31
|vpiSize:64
|UINT:31
|vpiRightRange:
\_constant: , id:44, line:85:23, endln:85:24
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiStmt:
\_assignment: , id:621, line:89:5, endln:89:76, parent:work@dut.gen_modules[0].module_in_genscope, parID:594
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_operation: , id:623, line:89:19, endln:89:44, parID:621
|vpiOpType:24
|vpiOperand:
\_part_select: , id:624, line:89:19, endln:89:44, parent:work@ibex_counter.counter, parID:625
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:625, parent:work@ibex_counter.counter, parID:58
|vpiLeftRange:
\_operation: , id:626, line:89:27, endln:89:39, parID:624
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter.CounterWidth), id:627, line:89:27, endln:89:39, parID:626
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:528, line:58:17, endln:58:34, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:CounterWidth
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.CounterWidth
|UINT:32
|vpiTypespec:
\_int_typespec: (CounterWidth), id:454, line:58:13, endln:58:16, parent:work@dut.gen_modules[0].module_in_genscope.CounterWidth, parID:453
|vpiName:CounterWidth
|vpiOperand:
\_constant: , id:55, line:89:40, endln:89:41, parID:54
|vpiConstType:9
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiRightRange:
\_constant: , id:56, line:89:42, endln:89:43
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiOperand:
\_operation: , id:628, line:89:47, endln:89:76, parID:623
|vpiOpType:33
|vpiOperand:
\_operation: , id:629, line:89:48, endln:89:70, parID:628
|vpiOpType:34
|vpiOperand:
\_operation: , id:630, line:89:49, endln:89:61, parID:629
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:631, line:89:49, endln:89:61, parID:630
|vpiName:CounterWidth
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:528, line:58:17, endln:58:34, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiOperand:
\_constant: , id:63, line:89:62, endln:89:63, parID:62
|vpiConstType:9
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiOperand:
\_operation: , id:632, line:89:64, endln:89:68, parID:629
|vpiOpType:33
|vpiOperand:
\_constant: , id:65, line:89:64, endln:89:68
|vpiConstType:3
|vpiDecompile:1'b0
|vpiSize:1
|BIN:0
|vpiOperand:
\_constant: , id:66, line:89:71, endln:89:75
|vpiConstType:3
|vpiDecompile:1'b1
|vpiSize:1
|BIN:1
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_upd), id:622, line:89:5, endln:89:16, parID:621
|vpiName:counter_upd
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_upd
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_upd), id:517, line:71:28, endln:71:39, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_upd
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_upd
|vpiNetType:36
|vpiRange:
\_range: , id:518, line:71:10, endln:71:26, parent:work@dut.gen_modules[0].module_in_genscope.counter_upd, parID:517
|vpiLeftRange:
\_constant: , id:208, line:71:10, endln:71:22, parID:204
|vpiConstType:7
|vpiDecompile:9
|vpiSize:64
|INT:9
|vpiRightRange:
\_constant: , id:209, line:71:25, endln:71:26, parID:204
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiStmt:
\_if_else: , id:633, line:92:5, endln:98:8, parent:work@dut.gen_modules[0].module_in_genscope, parID:594
|vpiCondition:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.we), id:634, line:92:9, endln:92:11, parID:633
|vpiName:we
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.we
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.we), id:521, line:73:28, endln:73:30, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:635, line:92:13, endln:94:8, parID:633
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_assignment: , id:636, line:93:7, endln:93:49, parent:work@dut.gen_modules[0].module_in_genscope, parID:635
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:638, line:93:19, endln:93:49, parent:work@ibex_counter.counter_load, parID:639
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:639, parent:work@ibex_counter.counter_load, parID:78
|vpiLeftRange:
\_operation: , id:640, line:93:32, endln:93:44, parID:638
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter_load.CounterWidth), id:641, line:93:32, endln:93:44, parID:640
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter_load.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:528, line:58:17, endln:58:34, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiOperand:
\_constant: , id:75, line:93:45, endln:93:46, parID:74
|vpiConstType:9
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiRightRange:
\_constant: , id:76, line:93:47, endln:93:48
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:637, line:93:7, endln:93:16, parID:636
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:522, line:74:28, endln:74:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_d
|vpiNetType:36
|vpiRange:
\_range: , id:523, line:74:10, endln:74:26, parent:work@dut.gen_modules[0].module_in_genscope.counter_d, parID:522
|vpiLeftRange:
\_constant: , id:220, line:74:10, endln:74:22, parID:216
|vpiConstType:7
|vpiDecompile:9
|vpiSize:64
|INT:9
|vpiRightRange:
\_constant: , id:221, line:74:25, endln:74:26, parID:216
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiElseStmt:
\_if_else: , id:642, line:94:18, endln:94:31, parID:633
|vpiCondition:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_inc_i), id:643, line:94:18, endln:94:31, parID:642
|vpiName:counter_inc_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_inc_i
|vpiActual:
\_logic_net: (work@dut.counter_inc_i), id:136, line:36:24, endln:36:37, parent:work@dut, parID:444
|vpiStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:644, line:94:32, endln:96:8, parID:642
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_assignment: , id:645, line:95:7, endln:95:48, parent:work@dut.gen_modules[0].module_in_genscope, parID:644
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:647, line:95:19, endln:95:48, parent:work@ibex_counter.counter_upd, parID:648
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_upd), id:648, parent:work@ibex_counter.counter_upd, parID:89
|vpiLeftRange:
\_operation: , id:649, line:95:31, endln:95:43, parID:647
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter_upd.CounterWidth), id:650, line:95:31, endln:95:43, parID:649
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter_upd.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:528, line:58:17, endln:58:34, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiOperand:
\_constant: , id:86, line:95:44, endln:95:45, parID:85
|vpiConstType:9
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiRightRange:
\_constant: , id:87, line:95:46, endln:95:47
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:646, line:95:7, endln:95:16, parID:645
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:522, line:74:28, endln:74:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiElseStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:651, line:96:14, endln:98:8, parID:642
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_assignment: , id:652, line:97:7, endln:97:44, parent:work@dut.gen_modules[0].module_in_genscope, parID:651
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:654, line:97:19, endln:97:44, parent:work@ibex_counter.counter, parID:655
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:655, parent:work@ibex_counter.counter, parID:98
|vpiLeftRange:
\_operation: , id:656, line:97:27, endln:97:39, parID:654
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter.CounterWidth), id:657, line:97:27, endln:97:39, parID:656
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:528, line:58:17, endln:58:34, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiOperand:
\_constant: , id:95, line:97:40, endln:97:41, parID:94
|vpiConstType:9
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiRightRange:
\_constant: , id:96, line:97:42, endln:97:43
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:653, line:97:7, endln:97:16, parID:652
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:522, line:74:28, endln:74:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiProcess:
\_always: , id:658, line:115:3, endln:121:6, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , id:659, line:115:13, endln:121:6, parID:658
|vpiCondition:
\_operation: , id:660, line:115:15, endln:115:28, parID:659
|vpiOpType:35
|vpiOperand:
\_operation: , id:661, line:115:15, endln:115:22, parID:660
|vpiOpType:39
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.clk_i), id:662, line:115:23, endln:115:28, parID:661
|vpiName:clk_i
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.clk_i
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.clk_i), id:513, line:60:23, endln:60:28, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiOperand:
\_operation: , id:663, line:115:32, endln:115:39, parID:660
|vpiOpType:40
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.rst_ni), id:664, line:115:40, endln:115:46, parID:663
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.rst_ni
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.rst_ni), id:514, line:61:23, endln:61:29, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:665, line:115:48, endln:121:6, parID:659
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_if_else: , id:666, line:116:5, endln:120:8, parent:work@dut.gen_modules[0].module_in_genscope, parID:665
|vpiCondition:
\_operation: , id:667, line:116:9, endln:116:16, parID:666
|vpiOpType:3
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.rst_ni), id:668, line:116:10, endln:116:16, parID:667
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.rst_ni
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.rst_ni), id:514, line:61:23, endln:61:29, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:669, line:116:18, endln:118:8, parID:666
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_assignment: , id:670, line:117:7, endln:117:22, parent:work@dut.gen_modules[0].module_in_genscope, parID:669
|vpiOpType:82
|vpiRhs:
\_constant: , id:113, line:117:20, endln:117:22, parID:114
|vpiConstType:3
|vpiDecompile:'0
|vpiSize:-1
|BIN:0
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_q), id:671, line:117:7, endln:117:16, parID:670
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_q
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_q), id:524, line:109:28, endln:109:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_q
|vpiNetType:36
|vpiRange:
\_range: , id:525, line:109:10, endln:109:26, parent:work@dut.gen_modules[0].module_in_genscope.counter_q, parID:524
|vpiLeftRange:
\_constant: , id:227, line:109:10, endln:109:22, parID:223
|vpiConstType:7
|vpiDecompile:9
|vpiSize:64
|INT:9
|vpiRightRange:
\_constant: , id:228, line:109:25, endln:109:26, parID:223
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiElseStmt:
\_begin: (work@dut.gen_modules[0].module_in_genscope), id:672, line:118:14, endln:120:8, parID:666
|vpiFullName:work@dut.gen_modules[0].module_in_genscope
|vpiStmt:
\_assignment: , id:673, line:119:7, endln:119:29, parent:work@dut.gen_modules[0].module_in_genscope, parID:672
|vpiOpType:82
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:675, line:119:20, endln:119:29, parID:673
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:522, line:74:28, endln:74:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_q), id:674, line:119:7, endln:119:16, parID:673
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_q
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_q), id:524, line:109:28, endln:109:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiContAssign:
\_cont_assign: , id:707, line:133:10, endln:133:33, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter), id:708, line:133:26, endln:133:33, parID:707
|vpiName:counter
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter), id:515, line:70:28, endln:70:35, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter
|vpiNetType:36
|vpiRange:
\_range: , id:516, line:70:10, endln:70:14, parent:work@dut.gen_modules[0].module_in_genscope.counter, parID:515
|vpiLeftRange:
\_constant: , id:201, line:70:10, endln:70:12, parID:200
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:202, line:70:13, endln:70:14, parID:200
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.counter_val_o), id:709, line:133:10, endln:133:23, parID:707
|vpiName:counter_val_o
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_val_o
|vpiActual:
\_logic_net: (work@dut.counter_val_o), id:170, line:40:31, endln:40:44, parent:work@dut, parID:444
|vpiGenScopeArray:
\_gen_scope_array: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow), id:710, line:123:3, endln:131:6, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:g_counter_narrow
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow
|vpiGenScope:
\_gen_scope: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow), id:711, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow, parID:710
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.unused_counter_load), id:286, line:124:29, endln:124:48, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow, parID:456
|vpiName:unused_counter_load
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.unused_counter_load
|vpiNetType:36
|vpiRange:
\_range: , id:283, line:124:12, endln:124:27
|vpiLeftRange:
\_constant: , id:284, line:124:12, endln:124:14, parID:283
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:285, line:124:15, endln:124:27, parID:283
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiContAssign:
\_cont_assign: , id:712, line:126:12, endln:126:49, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow, parID:711
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter_q), id:713, line:126:40, endln:126:49, parID:712
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter_q
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_q), id:524, line:109:28, endln:109:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiLhs:
\_part_select: , id:714, line:126:12, endln:126:19, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter, parID:715
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter), id:715, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter, parID:504
|vpiLeftRange:
\_operation: , id:716, line:126:20, endln:126:32, parID:714
|vpiOpType:11
|vpiOperand:
\_constant: , id:258, line:126:20, endln:126:32, parID:260
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:259, line:58:13, endln:58:16, parID:258
|vpiName:CounterWidth
|vpiOperand:
\_constant: , id:261, line:126:33, endln:126:34, parID:260
|vpiConstType:9
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiRightRange:
\_constant: , id:262, line:126:35, endln:126:36
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiContAssign:
\_cont_assign: , id:717, line:127:12, endln:127:42, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow, parID:711
|vpiRhs:
\_constant: , id:272, line:127:40, endln:127:42, parID:273
|vpiConstType:3
|vpiDecompile:'0
|vpiSize:-1
|BIN:0
|vpiLhs:
\_part_select: , id:718, line:127:12, endln:127:19, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter, parID:719
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter), id:719, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter, parID:508
|vpiLeftRange:
\_constant: , id:267, line:127:20, endln:127:22
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:268, line:127:23, endln:127:35
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:269, line:58:13, endln:58:16, parID:268
|vpiName:CounterWidth
|vpiContAssign:
\_cont_assign: , id:720, line:128:12, endln:128:69, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow, parID:711
|vpiRhs:
\_part_select: , id:721, line:128:40, endln:128:69, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter_load, parID:722
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter_load), id:722, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.counter_load, parID:511
|vpiLeftRange:
\_constant: , id:275, line:128:53, endln:128:55
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:276, line:128:56, endln:128:68
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:277, line:58:13, endln:58:16, parID:276
|vpiName:CounterWidth
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.unused_counter_load), id:723, line:128:12, endln:128:31, parID:720
|vpiName:unused_counter_load
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.unused_counter_load
|vpiActual:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.g_counter_narrow.unused_counter_load), id:286, line:124:29, endln:124:48, parent:work@dut.gen_modules[0].module_in_genscope.g_counter_narrow, parID:456
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.clk_i), id:513, line:60:23, endln:60:28, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.rst_ni), id:514, line:61:23, endln:61:29, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiNet:
\_logic_net: (work@dut.counter_inc_i), id:136, line:36:24, endln:36:37, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_we_i), id:150, line:38:24, endln:38:36, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_val_o), id:170, line:40:31, endln:40:44, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter), id:515, line:70:28, endln:70:35, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_upd), id:517, line:71:28, endln:71:39, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_load), id:519, line:72:28, endln:72:40, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiName:counter_load
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.counter_load
|vpiNetType:36
|vpiRange:
\_range: , id:520, line:72:10, endln:72:14, parent:work@dut.gen_modules[0].module_in_genscope.counter_load, parID:519
|vpiLeftRange:
\_constant: , id:212, line:72:10, endln:72:12, parID:211
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:213, line:72:13, endln:72:14, parID:211
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.we), id:521, line:73:28, endln:73:30, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:522, line:74:28, endln:74:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_q), id:524, line:109:28, endln:109:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiParameter:
\_parameter: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:528, line:58:17, endln:58:34, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiParamAssign:
\_param_assign: , id:526, line:58:17, endln:58:34, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
|vpiRhs:
\_constant: , id:179, line:58:32, endln:58:34
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:8, line:58:13, endln:58:16, parent:work@ibex_counter.CounterWidth, parID:9
|vpiName:CounterWidth
|vpiLhs:
\_parameter: (work@dut.gen_modules[0].module_in_genscope.CounterWidth), id:527, line:58:17, endln:58:34, parID:526
|vpiName:CounterWidth
|vpiFullName:work@dut.gen_modules[0].module_in_genscope.CounterWidth
|UINT:32
|vpiTypespec:
\_int_typespec: (CounterWidth), id:454, line:58:13, endln:58:16, parent:work@dut.gen_modules[0].module_in_genscope.CounterWidth, parID:453
|vpiParameter:
\_parameter: (work@dut.gen_modules[0].i), id:451, line:41, parent:work@dut.gen_modules[0], parID:466
|vpiGenScopeArray:
\_gen_scope_array: (work@dut.gen_modules[1]), id:529, line:41:41, endln:51:4, parent:work@dut, parID:444
|vpiName:gen_modules[1]
|vpiFullName:work@dut.gen_modules[1]
|vpiGenScope:
\_gen_scope: (work@dut.gen_modules[1]), id:530, parent:work@dut.gen_modules[1], parID:529
|vpiFullName:work@dut.gen_modules[1]
|vpiModule:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiDefName:work@ibex_counter
|vpiDefFile:tests/ScratchPad.sv
|vpiDefLineNo:57
|vpiName:module_in_genscope
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiPort:
\_port: (clk_i), id:807, line:60:23, endln:60:28, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:clk_i
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (work@dut.gen_modules[1].clk), id:808, line:43:42, endln:43:45, parent:clk_i, parID:807
|vpiName:clk
|vpiFullName:work@dut.gen_modules[1].clk
|vpiActual:
\_logic_net: (work@dut.clk), id:128, line:34:7, endln:34:10, parent:work@dut, parID:444
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.clk_i), id:809, parent:clk_i, parID:807
|vpiName:clk_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.clk_i
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.clk_i), id:577, line:60:23, endln:60:28, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:clk_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.clk_i
|vpiNetType:36
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiPort:
\_port: (rst_ni), id:810, line:61:23, endln:61:29, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:rst_ni
|vpiDirection:1
|vpiHighConn:
\_ref_obj: (work@dut.gen_modules[1].rst), id:811, line:44:43, endln:44:46, parent:rst_ni, parID:810
|vpiName:rst
|vpiFullName:work@dut.gen_modules[1].rst
|vpiActual:
\_logic_net: (work@dut.rst), id:129, line:35:7, endln:35:10, parent:work@dut, parID:444
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.rst_ni), id:812, parent:rst_ni, parID:810
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.rst_ni
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.rst_ni), id:578, line:61:23, endln:61:29, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.rst_ni
|vpiNetType:36
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiPort:
\_port: (counter_inc_i), id:813, line:63:23, endln:63:36, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_inc_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counter_inc_i), id:814, line:45:50, endln:45:66, parent:counter_inc_i, parID:815
|vpiName:counter_inc_i
|vpiFullName:work@dut.counter_inc_i
|vpiIndex:
\_ref_obj: (counter_inc_i.i), id:816, line:45:64, endln:45:65, parent:work@dut.counter_inc_i, parID:814
|vpiName:i
|vpiFullName:counter_inc_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[1].i), id:459, line:41, parent:work@dut.gen_modules[1], parID:530
|vpiName:i
|vpiFullName:work@dut.gen_modules[1].i
|UINT:1
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_inc_i), id:817, parent:counter_inc_i, parID:813
|vpiName:counter_inc_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_inc_i
|vpiActual:
\_logic_net: (work@dut.counter_inc_i), id:136, line:36:24, endln:36:37, parent:work@dut, parID:444
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiPort:
\_port: (counterh_we_i), id:818, line:64:23, endln:64:36, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counterh_we_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counterh_we_i), id:819, line:46:50, endln:46:66, parent:counterh_we_i, parID:820
|vpiName:counterh_we_i
|vpiFullName:work@dut.counterh_we_i
|vpiIndex:
\_ref_obj: (counterh_we_i.i), id:821, line:46:64, endln:46:65, parent:work@dut.counterh_we_i, parID:819
|vpiName:i
|vpiFullName:counterh_we_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[1].i), id:459, line:41, parent:work@dut.gen_modules[1], parID:530
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counterh_we_i), id:822, parent:counterh_we_i, parID:818
|vpiName:counterh_we_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counterh_we_i
|vpiActual:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiPort:
\_port: (counter_we_i), id:823, line:65:23, endln:65:35, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_we_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counter_we_i), id:824, line:47:49, endln:47:64, parent:counter_we_i, parID:825
|vpiName:counter_we_i
|vpiFullName:work@dut.counter_we_i
|vpiIndex:
\_ref_obj: (counter_we_i.i), id:826, line:47:62, endln:47:63, parent:work@dut.counter_we_i, parID:824
|vpiName:i
|vpiFullName:counter_we_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[1].i), id:459, line:41, parent:work@dut.gen_modules[1], parID:530
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_we_i), id:827, parent:counter_we_i, parID:823
|vpiName:counter_we_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_we_i
|vpiActual:
\_logic_net: (work@dut.counter_we_i), id:150, line:38:24, endln:38:36, parent:work@dut, parID:444
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiPort:
\_port: (counter_val_i), id:828, line:66:23, endln:66:36, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_val_i
|vpiDirection:1
|vpiHighConn:
\_bit_select: (work@dut.counter_val_i), id:829, line:48:50, endln:48:66, parent:counter_val_i, parID:830
|vpiName:counter_val_i
|vpiFullName:work@dut.counter_val_i
|vpiIndex:
\_ref_obj: (counter_val_i.i), id:831, line:48:64, endln:48:65, parent:work@dut.counter_val_i, parID:829
|vpiName:i
|vpiFullName:counter_val_i.i
|vpiActual:
\_parameter: (work@dut.gen_modules[1].i), id:459, line:41, parent:work@dut.gen_modules[1], parID:530
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_val_i), id:832, parent:counter_val_i, parID:828
|vpiName:counter_val_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_val_i
|vpiActual:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiPort:
\_port: (counter_val_o), id:833, line:67:23, endln:67:36, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_val_o
|vpiDirection:2
|vpiHighConn:
\_bit_select: (work@dut.counter_val_o), id:834, line:49:50, endln:49:66, parent:counter_val_o, parID:835
|vpiName:counter_val_o
|vpiFullName:work@dut.counter_val_o
|vpiIndex:
\_ref_obj: (counter_val_o.i), id:836, line:49:64, endln:49:65, parent:work@dut.counter_val_o, parID:834
|vpiName:i
|vpiFullName:counter_val_o.i
|vpiActual:
\_parameter: (work@dut.gen_modules[1].i), id:459, line:41, parent:work@dut.gen_modules[1], parID:530
|vpiLowConn:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_val_o), id:837, parent:counter_val_o, parID:833
|vpiName:counter_val_o
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_val_o
|vpiActual:
\_logic_net: (work@dut.counter_val_o), id:170, line:40:31, endln:40:44, parent:work@dut, parID:444
|vpiInstance:
\_module: work@ibex_counter (work@dut.gen_modules[1].module_in_genscope), id:531 tests/ScratchPad.sv:42:3: , endln:50:35, parent:work@dut.gen_modules[1], parID:530
|vpiProcess:
\_always: , id:724, line:77:3, endln:99:6, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiAlwaysType:2
|vpiStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:725, line:77:15, endln:99:6, parID:724
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_assignment: , id:726, line:80:5, endln:80:38, parent:work@dut.gen_modules[1].module_in_genscope, parID:725
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_operation: , id:728, line:80:10, endln:80:22, parID:726
|vpiOpType:29
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_we_i), id:729, line:80:10, endln:80:22, parID:728
|vpiName:counter_we_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_we_i
|vpiActual:
\_logic_net: (work@dut.counter_we_i), id:150, line:38:24, endln:38:36, parent:work@dut, parID:444
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counterh_we_i), id:730, line:80:25, endln:80:38, parID:728
|vpiName:counterh_we_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counterh_we_i
|vpiActual:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.we), id:727, line:80:5, endln:80:7, parID:726
|vpiName:we
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.we
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.we), id:585, line:73:28, endln:73:30, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:we
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.we
|vpiNetType:36
|vpiStmt:
\_assignment: , id:731, line:81:5, endln:81:41, parent:work@dut.gen_modules[1].module_in_genscope, parID:725
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:734, line:81:27, endln:81:41, parent:work@ibex_counter.counter, parID:735
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:735, parent:work@ibex_counter.counter, parID:26
|vpiLeftRange:
\_constant: , id:23, line:81:35, endln:81:37
|vpiRightRange:
\_constant: , id:24, line:81:38, endln:81:40
|vpiLhs:
\_part_select: , id:732, line:81:5, endln:81:17, parent:work@ibex_counter.counter_load, parID:733
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:733, parent:work@ibex_counter.counter_load, parID:22
|vpiLeftRange:
\_constant: , id:19, line:81:18, endln:81:20
|vpiRightRange:
\_constant: , id:20, line:81:21, endln:81:23
|vpiStmt:
\_assignment: , id:736, line:82:5, endln:82:40, parent:work@dut.gen_modules[1].module_in_genscope, parID:725
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_val_i), id:739, line:82:27, endln:82:40, parID:736
|vpiName:counter_val_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_val_i
|vpiActual:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiLhs:
\_part_select: , id:737, line:82:5, endln:82:17, parent:work@ibex_counter.counter_load, parID:738
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:738, parent:work@ibex_counter.counter_load, parID:31
|vpiLeftRange:
\_constant: , id:28, line:82:18, endln:82:20
|vpiRightRange:
\_constant: , id:29, line:82:21, endln:82:22
|vpiStmt:
\_if_stmt: , id:740, line:83:5, endln:86:8, parent:work@dut.gen_modules[1].module_in_genscope, parID:725
|vpiCondition:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counterh_we_i), id:741, line:83:9, endln:83:22, parID:740
|vpiName:counterh_we_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counterh_we_i
|vpiActual:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:742, line:83:24, endln:86:8, parID:740
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_assignment: , id:743, line:84:7, endln:84:42, parent:work@dut.gen_modules[1].module_in_genscope, parID:742
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_val_i), id:746, line:84:29, endln:84:42, parID:743
|vpiName:counter_val_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_val_i
|vpiActual:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiLhs:
\_part_select: , id:744, line:84:7, endln:84:19, parent:work@ibex_counter.counter_load, parID:745
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:745, parent:work@ibex_counter.counter_load, parID:40
|vpiLeftRange:
\_constant: , id:37, line:84:20, endln:84:22
|vpiRightRange:
\_constant: , id:38, line:84:23, endln:84:25
|vpiStmt:
\_assignment: , id:747, line:85:7, endln:85:42, parent:work@dut.gen_modules[1].module_in_genscope, parID:742
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:750, line:85:29, endln:85:42, parent:work@ibex_counter.counter, parID:751
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:751, parent:work@ibex_counter.counter, parID:50
|vpiLeftRange:
\_constant: , id:47, line:85:37, endln:85:39
|vpiRightRange:
\_constant: , id:48, line:85:40, endln:85:41
|vpiLhs:
\_part_select: , id:748, line:85:7, endln:85:19, parent:work@ibex_counter.counter_load, parID:749
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:749, parent:work@ibex_counter.counter_load, parID:46
|vpiLeftRange:
\_constant: , id:43, line:85:20, endln:85:22
|vpiRightRange:
\_constant: , id:44, line:85:23, endln:85:24
|vpiStmt:
\_assignment: , id:752, line:89:5, endln:89:76, parent:work@dut.gen_modules[1].module_in_genscope, parID:725
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_operation: , id:754, line:89:19, endln:89:44, parID:752
|vpiOpType:24
|vpiOperand:
\_part_select: , id:755, line:89:19, endln:89:44, parent:work@ibex_counter.counter, parID:756
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:756, parent:work@ibex_counter.counter, parID:58
|vpiLeftRange:
\_operation: , id:757, line:89:27, endln:89:39, parID:755
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter.CounterWidth), id:758, line:89:27, endln:89:39, parID:757
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:592, line:58:17, endln:58:34, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:CounterWidth
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.CounterWidth
|UINT:32
|vpiTypespec:
\_int_typespec: (CounterWidth), id:462, line:58:13, endln:58:16, parent:work@dut.gen_modules[1].module_in_genscope.CounterWidth, parID:461
|vpiName:CounterWidth
|vpiOperand:
\_constant: , id:55, line:89:40, endln:89:41, parID:54
|vpiRightRange:
\_constant: , id:56, line:89:42, endln:89:43
|vpiOperand:
\_operation: , id:759, line:89:47, endln:89:76, parID:754
|vpiOpType:33
|vpiOperand:
\_operation: , id:760, line:89:48, endln:89:70, parID:759
|vpiOpType:34
|vpiOperand:
\_operation: , id:761, line:89:49, endln:89:61, parID:760
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:762, line:89:49, endln:89:61, parID:761
|vpiName:CounterWidth
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:592, line:58:17, endln:58:34, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiOperand:
\_constant: , id:63, line:89:62, endln:89:63, parID:62
|vpiOperand:
\_operation: , id:763, line:89:64, endln:89:68, parID:760
|vpiOpType:33
|vpiOperand:
\_constant: , id:65, line:89:64, endln:89:68
|vpiOperand:
\_constant: , id:66, line:89:71, endln:89:75
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_upd), id:753, line:89:5, endln:89:16, parID:752
|vpiName:counter_upd
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_upd
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_upd), id:581, line:71:28, endln:71:39, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_upd
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_upd
|vpiNetType:36
|vpiRange:
\_range: , id:582, line:71:10, endln:71:26, parent:work@dut.gen_modules[1].module_in_genscope.counter_upd, parID:581
|vpiLeftRange:
\_constant: , id:324, line:71:10, endln:71:22, parID:320
|vpiConstType:7
|vpiDecompile:9
|vpiSize:64
|INT:9
|vpiRightRange:
\_constant: , id:325, line:71:25, endln:71:26, parID:320
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiStmt:
\_if_else: , id:764, line:92:5, endln:98:8, parent:work@dut.gen_modules[1].module_in_genscope, parID:725
|vpiCondition:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.we), id:765, line:92:9, endln:92:11, parID:764
|vpiName:we
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.we
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.we), id:585, line:73:28, endln:73:30, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:766, line:92:13, endln:94:8, parID:764
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_assignment: , id:767, line:93:7, endln:93:49, parent:work@dut.gen_modules[1].module_in_genscope, parID:766
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:769, line:93:19, endln:93:49, parent:work@ibex_counter.counter_load, parID:770
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_load), id:770, parent:work@ibex_counter.counter_load, parID:78
|vpiLeftRange:
\_operation: , id:771, line:93:32, endln:93:44, parID:769
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter_load.CounterWidth), id:772, line:93:32, endln:93:44, parID:771
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter_load.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:592, line:58:17, endln:58:34, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiOperand:
\_constant: , id:75, line:93:45, endln:93:46, parID:74
|vpiRightRange:
\_constant: , id:76, line:93:47, endln:93:48
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:768, line:93:7, endln:93:16, parID:767
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:586, line:74:28, endln:74:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_d
|vpiNetType:36
|vpiRange:
\_range: , id:587, line:74:10, endln:74:26, parent:work@dut.gen_modules[1].module_in_genscope.counter_d, parID:586
|vpiLeftRange:
\_constant: , id:336, line:74:10, endln:74:22, parID:332
|vpiConstType:7
|vpiDecompile:9
|vpiSize:64
|INT:9
|vpiRightRange:
\_constant: , id:337, line:74:25, endln:74:26, parID:332
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiElseStmt:
\_if_else: , id:773, line:94:18, endln:94:31, parID:764
|vpiCondition:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_inc_i), id:774, line:94:18, endln:94:31, parID:773
|vpiName:counter_inc_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_inc_i
|vpiActual:
\_logic_net: (work@dut.counter_inc_i), id:136, line:36:24, endln:36:37, parent:work@dut, parID:444
|vpiStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:775, line:94:32, endln:96:8, parID:773
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_assignment: , id:776, line:95:7, endln:95:48, parent:work@dut.gen_modules[1].module_in_genscope, parID:775
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:778, line:95:19, endln:95:48, parent:work@ibex_counter.counter_upd, parID:779
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter_upd), id:779, parent:work@ibex_counter.counter_upd, parID:89
|vpiLeftRange:
\_operation: , id:780, line:95:31, endln:95:43, parID:778
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter_upd.CounterWidth), id:781, line:95:31, endln:95:43, parID:780
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter_upd.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:592, line:58:17, endln:58:34, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiOperand:
\_constant: , id:86, line:95:44, endln:95:45, parID:85
|vpiRightRange:
\_constant: , id:87, line:95:46, endln:95:47
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:777, line:95:7, endln:95:16, parID:776
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:586, line:74:28, endln:74:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiElseStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:782, line:96:14, endln:98:8, parID:773
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_assignment: , id:783, line:97:7, endln:97:44, parent:work@dut.gen_modules[1].module_in_genscope, parID:782
|vpiOpType:82
|vpiBlocking:1
|vpiRhs:
\_part_select: , id:785, line:97:19, endln:97:44, parent:work@ibex_counter.counter, parID:786
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@ibex_counter.counter), id:786, parent:work@ibex_counter.counter, parID:98
|vpiLeftRange:
\_operation: , id:787, line:97:27, endln:97:39, parID:785
|vpiOpType:11
|vpiOperand:
\_ref_obj: (work@ibex_counter.counter.CounterWidth), id:788, line:97:27, endln:97:39, parID:787
|vpiName:CounterWidth
|vpiFullName:work@ibex_counter.counter.CounterWidth
|vpiActual:
\_parameter: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:592, line:58:17, endln:58:34, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiOperand:
\_constant: , id:95, line:97:40, endln:97:41, parID:94
|vpiRightRange:
\_constant: , id:96, line:97:42, endln:97:43
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:784, line:97:7, endln:97:16, parID:783
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:586, line:74:28, endln:74:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiProcess:
\_always: , id:789, line:115:3, endln:121:6, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiAlwaysType:3
|vpiStmt:
\_event_control: , id:790, line:115:13, endln:121:6, parID:789
|vpiCondition:
\_operation: , id:791, line:115:15, endln:115:28, parID:790
|vpiOpType:35
|vpiOperand:
\_operation: , id:792, line:115:15, endln:115:22, parID:791
|vpiOpType:39
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.clk_i), id:793, line:115:23, endln:115:28, parID:792
|vpiName:clk_i
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.clk_i
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.clk_i), id:577, line:60:23, endln:60:28, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiOperand:
\_operation: , id:794, line:115:32, endln:115:39, parID:791
|vpiOpType:40
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.rst_ni), id:795, line:115:40, endln:115:46, parID:794
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.rst_ni
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.rst_ni), id:578, line:61:23, endln:61:29, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:796, line:115:48, endln:121:6, parID:790
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_if_else: , id:797, line:116:5, endln:120:8, parent:work@dut.gen_modules[1].module_in_genscope, parID:796
|vpiCondition:
\_operation: , id:798, line:116:9, endln:116:16, parID:797
|vpiOpType:3
|vpiOperand:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.rst_ni), id:799, line:116:10, endln:116:16, parID:798
|vpiName:rst_ni
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.rst_ni
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.rst_ni), id:578, line:61:23, endln:61:29, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:800, line:116:18, endln:118:8, parID:797
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_assignment: , id:801, line:117:7, endln:117:22, parent:work@dut.gen_modules[1].module_in_genscope, parID:800
|vpiOpType:82
|vpiRhs:
\_constant: , id:113, line:117:20, endln:117:22, parID:114
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_q), id:802, line:117:7, endln:117:16, parID:801
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_q
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_q), id:588, line:109:28, endln:109:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_q
|vpiNetType:36
|vpiRange:
\_range: , id:589, line:109:10, endln:109:26, parent:work@dut.gen_modules[1].module_in_genscope.counter_q, parID:588
|vpiLeftRange:
\_constant: , id:343, line:109:10, endln:109:22, parID:339
|vpiConstType:7
|vpiDecompile:9
|vpiSize:64
|INT:9
|vpiRightRange:
\_constant: , id:344, line:109:25, endln:109:26, parID:339
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiElseStmt:
\_begin: (work@dut.gen_modules[1].module_in_genscope), id:803, line:118:14, endln:120:8, parID:797
|vpiFullName:work@dut.gen_modules[1].module_in_genscope
|vpiStmt:
\_assignment: , id:804, line:119:7, endln:119:29, parent:work@dut.gen_modules[1].module_in_genscope, parID:803
|vpiOpType:82
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:806, line:119:20, endln:119:29, parID:804
|vpiName:counter_d
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_d
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:586, line:74:28, endln:74:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_q), id:805, line:119:7, endln:119:16, parID:804
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_q
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_q), id:588, line:109:28, endln:109:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiContAssign:
\_cont_assign: , id:838, line:133:10, endln:133:33, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter), id:839, line:133:26, endln:133:33, parID:838
|vpiName:counter
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter), id:579, line:70:28, endln:70:35, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter
|vpiNetType:36
|vpiRange:
\_range: , id:580, line:70:10, endln:70:14, parent:work@dut.gen_modules[1].module_in_genscope.counter, parID:579
|vpiLeftRange:
\_constant: , id:317, line:70:10, endln:70:12, parID:316
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:318, line:70:13, endln:70:14, parID:316
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.counter_val_o), id:840, line:133:10, endln:133:23, parID:838
|vpiName:counter_val_o
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_val_o
|vpiActual:
\_logic_net: (work@dut.counter_val_o), id:170, line:40:31, endln:40:44, parent:work@dut, parID:444
|vpiGenScopeArray:
\_gen_scope_array: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow), id:841, line:123:3, endln:131:6, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:g_counter_narrow
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow
|vpiGenScope:
\_gen_scope: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow), id:842, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow, parID:841
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.unused_counter_load), id:402, line:124:29, endln:124:48, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow, parID:464
|vpiName:unused_counter_load
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.unused_counter_load
|vpiNetType:36
|vpiRange:
\_range: , id:399, line:124:12, endln:124:27
|vpiLeftRange:
\_constant: , id:400, line:124:12, endln:124:14, parID:399
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:401, line:124:15, endln:124:27, parID:399
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiContAssign:
\_cont_assign: , id:843, line:126:12, endln:126:49, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow, parID:842
|vpiRhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter_q), id:844, line:126:40, endln:126:49, parID:843
|vpiName:counter_q
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter_q
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_q), id:588, line:109:28, endln:109:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiLhs:
\_part_select: , id:845, line:126:12, endln:126:19, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter, parID:846
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter), id:846, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter, parID:568
|vpiLeftRange:
\_operation: , id:847, line:126:20, endln:126:32, parID:845
|vpiOpType:11
|vpiOperand:
\_constant: , id:374, line:126:20, endln:126:32, parID:376
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:375, line:58:13, endln:58:16, parID:374
|vpiName:CounterWidth
|vpiOperand:
\_constant: , id:377, line:126:33, endln:126:34, parID:376
|vpiConstType:9
|vpiDecompile:1
|vpiSize:64
|UINT:1
|vpiRightRange:
\_constant: , id:378, line:126:35, endln:126:36
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiContAssign:
\_cont_assign: , id:848, line:127:12, endln:127:42, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow, parID:842
|vpiRhs:
\_constant: , id:388, line:127:40, endln:127:42, parID:389
|vpiConstType:3
|vpiDecompile:'0
|vpiSize:-1
|BIN:0
|vpiLhs:
\_part_select: , id:849, line:127:12, endln:127:19, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter, parID:850
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter), id:850, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter, parID:572
|vpiLeftRange:
\_constant: , id:383, line:127:20, endln:127:22
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:384, line:127:23, endln:127:35
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:385, line:58:13, endln:58:16, parID:384
|vpiName:CounterWidth
|vpiContAssign:
\_cont_assign: , id:851, line:128:12, endln:128:69, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow, parID:842
|vpiRhs:
\_part_select: , id:852, line:128:40, endln:128:69, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter_load, parID:853
|vpiConstantSelect:1
|vpiParent:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter_load), id:853, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.counter_load, parID:575
|vpiLeftRange:
\_constant: , id:391, line:128:53, endln:128:55
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:392, line:128:56, endln:128:68
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:393, line:58:13, endln:58:16, parID:392
|vpiName:CounterWidth
|vpiLhs:
\_ref_obj: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.unused_counter_load), id:854, line:128:12, endln:128:31, parID:851
|vpiName:unused_counter_load
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.unused_counter_load
|vpiActual:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.g_counter_narrow.unused_counter_load), id:402, line:124:29, endln:124:48, parent:work@dut.gen_modules[1].module_in_genscope.g_counter_narrow, parID:464
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.clk_i), id:577, line:60:23, endln:60:28, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.rst_ni), id:578, line:61:23, endln:61:29, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiNet:
\_logic_net: (work@dut.counter_inc_i), id:136, line:36:24, endln:36:37, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_we_i), id:150, line:38:24, endln:38:36, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_val_o), id:170, line:40:31, endln:40:44, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter), id:579, line:70:28, endln:70:35, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_upd), id:581, line:71:28, endln:71:39, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_load), id:583, line:72:28, endln:72:40, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiName:counter_load
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.counter_load
|vpiNetType:36
|vpiRange:
\_range: , id:584, line:72:10, endln:72:14, parent:work@dut.gen_modules[1].module_in_genscope.counter_load, parID:583
|vpiLeftRange:
\_constant: , id:328, line:72:10, endln:72:12, parID:327
|vpiConstType:9
|vpiDecompile:63
|vpiSize:64
|UINT:63
|vpiRightRange:
\_constant: , id:329, line:72:13, endln:72:14, parID:327
|vpiConstType:9
|vpiDecompile:0
|vpiSize:64
|UINT:0
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.we), id:585, line:73:28, endln:73:30, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_d), id:586, line:74:28, endln:74:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiNet:
\_logic_net: (work@dut.gen_modules[1].module_in_genscope.counter_q), id:588, line:109:28, endln:109:37, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiParameter:
\_parameter: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:592, line:58:17, endln:58:34, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiParamAssign:
\_param_assign: , id:590, line:58:17, endln:58:34, parent:work@dut.gen_modules[1].module_in_genscope, parID:531
|vpiRhs:
\_constant: , id:295, line:58:32, endln:58:34
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (CounterWidth), id:8, line:58:13, endln:58:16, parent:work@ibex_counter.CounterWidth, parID:9
|vpiLhs:
\_parameter: (work@dut.gen_modules[1].module_in_genscope.CounterWidth), id:591, line:58:17, endln:58:34, parID:590
|vpiName:CounterWidth
|vpiFullName:work@dut.gen_modules[1].module_in_genscope.CounterWidth
|UINT:32
|vpiTypespec:
\_int_typespec: (CounterWidth), id:462, line:58:13, endln:58:16, parent:work@dut.gen_modules[1].module_in_genscope.CounterWidth, parID:461
|vpiParameter:
\_parameter: (work@dut.gen_modules[1].i), id:459, line:41, parent:work@dut.gen_modules[1], parID:530
|vpiNet:
\_logic_net: (work@dut.clk), id:128, line:34:7, endln:34:10, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.rst), id:129, line:35:7, endln:35:10, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_inc_i), id:136, line:36:24, endln:36:37, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counterh_we_i), id:143, line:37:24, endln:37:37, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_we_i), id:150, line:38:24, endln:38:36, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_val_i), id:160, line:39:31, endln:39:44, parent:work@dut, parID:444
|vpiNet:
\_logic_net: (work@dut.counter_val_o), id:170, line:40:31, endln:40:44, parent:work@dut, parID:444
|vpiParameter:
\_parameter: (work@dut.NUM_MODULES), id:445, line:32:15, endln:32:30, parent:work@dut, parID:444
|vpiName:NUM_MODULES
|vpiFullName:work@dut.NUM_MODULES
|UINT:2
|vpiTypespec:
\_int_typespec: (NUM_MODULES), id:446, line:32:11, endln:32:14, parent:work@dut.NUM_MODULES, parID:445
|vpiName:NUM_MODULES
|vpiParameter:
\_parameter: (work@dut.MODULE_PARAM), id:447, line:33:15, endln:33:32, parent:work@dut, parID:444
|vpiName:MODULE_PARAM
|vpiFullName:work@dut.MODULE_PARAM
|UINT:10
|vpiTypespec:
\_int_typespec: (MODULE_PARAM), id:448, line:33:11, endln:33:14, parent:work@dut.MODULE_PARAM, parID:447
|vpiName:MODULE_PARAM
|vpiParamAssign:
\_param_assign: , id:124, line:32:15, endln:32:30, parent:work@dut, parID:444
|vpiRhs:
\_constant: , id:125, line:32:29, endln:32:30
|vpiConstType:9
|vpiDecompile:2
|vpiSize:64
|UINT:2
|vpiTypespec:
\_int_typespec: (NUM_MODULES), id:0, line:32:11, endln:32:14, parent:work@dut.NUM_MODULES, parID:1
|vpiName:NUM_MODULES
|vpiLhs:
\_parameter: (work@dut.NUM_MODULES), id:445, line:32:15, endln:32:30, parent:work@dut, parID:444
|vpiParamAssign:
\_param_assign: , id:126, line:33:15, endln:33:32, parent:work@dut, parID:444
|vpiRhs:
\_constant: , id:127, line:33:30, endln:33:32
|vpiConstType:9
|vpiDecompile:10
|vpiSize:64
|UINT:10
|vpiTypespec:
\_int_typespec: (MODULE_PARAM), id:4, line:33:11, endln:33:14, parent:work@dut.MODULE_PARAM, parID:5
|vpiName:MODULE_PARAM
|vpiLhs:
\_parameter: (work@dut.MODULE_PARAM), id:447, line:33:15, endln:33:32, parent:work@dut, parID:444
No problem, thanks for following up. I think I understand the two different modes now, and the additions to the README are helpful. I'll ask more questions as I run into them.
Also as a side note, my original point about the nets instead of variables still stands. The original code declares a variable (just picking one as an example):
logic [CounterWidth-1:0] counter_d;
but the UHDM dump has it as a net instead:
vpiNet:
\_logic_net: (work@dut.gen_modules[0].module_in_genscope.counter_d), id:522, line:74:28, endln:74:37, parent:work@dut.gen_modules[0].module_in_genscope, parID:467
Got it now. Since Surelog does not do driver/load analysis as of now, it can't know if he usage of a variable and assumes everything that is declared as a logic is a net.
I'm not sure the standard is very explicit here, but for something to be a variable and not a net it has to be a local usage (hence you have to perform some form of traversal to figure it out). Lacking that knowledge, Surelog assumes all logic types are nets.
If you have a better semantic interpretation that does not require a traversal of the driver/load please share! I'll be happy to implement the same
Oh, it's much simpler than that. A net declaration has a net type specified, and otherwise it's a variable. logic is a data type, not a net type, so the declaration is a variable. Net types are things like "wire", "tri", etc. You do need to handle user-defined nettypes but they are very rare in practice.
OK, let's spec it out:
wire a; // net
wire logic b; // net
logic c; // var logic
var d; // var logic
module top (input logic in); // wire ?
Page 704 of the 2017 standard has a lot of examples where ports of type wire are equivalent to "wire logic".
module mh0 (wire x); // inout wire logic x
module mh1 (integer x); // inout wire integer x
module mh2 (inout integer x); // inout wire integer x
module mh3 ([5:0] x); // inout wire logic [5:0] x
module mh4 (var x); // ERROR: direction defaults to inout which cannot be var
module mh5 (input x); // input wire logic x
module mh6 (input var x); // input var logic x
module mh7 (input var integer x); // input var integer x
module mh8 (output x); // output wire logic x
module mh9 (output var x); // output var logic x
module mh10(output signed [5:0] x); // output wire logic signed [5:0] x
module mh11(output integer x); // output var integer x
module mh12(ref [5:0] x); // ref var logic [5:0] x
module mh13(ref x [5:0]); // ref var logic x [5:0]
module mh14(wire x, y[7:0]); // inout wire logic x, inout wire logic y[7:0]
module mh15(integer x, signed [5:0] y); // inout wire integer x, inout wire logic signed [5:0] y
module mh16([5:0] x, wire y); // inout wire logic [5:0] x, inout wire logic y
module mh17(input var integer x, wire y); // input var integer x, input wire logic y
module mh18(output var x, input y); // output var logic x, input wire logic y
module mh19(output signed [5:0] x, integer y); // output wire logic signed [5:0] x, output var integer y
module mh20(ref [5:0] x, y); // ref var logic [5:0] x, ref var logic [5:0] y
module mh21(ref x [5:0], y); // ref var logic x [5:0], ref var logic y
Yes, that's right. The rules for ports are more complicated as you mention but still fully determined by the declaration itself and not how they are used. 23.2.2.3 has the algorithm for determining net vs variable for ports when not explicitly specified.
The following put request: "fix net var to match standard chipsalliance/Surelog#1809" should fix this issue.
I created a test that tests all the major possibilities:
https://github.com/chipsalliance/Surelog/tree/master/tests/StandardNetVar
@MikePopoloski, coming back to this after a while, sorry...
I changed the README to have more explanations.
I also realized the the Antmicro team is not using the -elabuhdm Surelog option which does bloat the memory, but also does what you are looking for.
That option (modulo bugs I'd be happy to fix) does indeed clone all objects including processes.
So on the example you are pointing out,
....
I'm trying to replicate the kind of output you got here -- with the scope hierarchy. Using uhdm-dump surelog.uhdm, I'm able to see it. I am doing pretty much the same thing done in UHDM/util/uhdm-dump.cpp in Surelog/src/hellouhdm.cpp -- that is vpi_iterate through vpiNets and use vpi_get_str(vpiFullName, <handle of ref_obj>);
All I get arework@<module name>.<local names of variables> instead of work@<top module name>.<inst name of child>.<local child variable>
Any idea what could be going wrong?
You are navigating the vpiAllModules instead of the vpiTopModules top level iterator.
From the vpiTopModules, you can recusvely traverse the sub instance and get handles on signals. You can use the vpiFullName attribute or you can also build hierarchical names yourself while doing the traversal (Keep track of your hierarchy instance name).
If you send snippet of code, it would be easier to point to the issues.
Yeah, works with uhdmtopModules. So, just to conclude:
We gotta walk the uhdmtopModules tree for full hierarchical names of nets/regs. If we also need, say, all the ternary statements these variables appear in, we'd have to switch to the uhdmallModules and look for continuous and procedural assignments that use ternaries, and get the local names of nets/regs, but save the corresponding full names from uhdmtopModules. Does that sound correct?
If so, is there any {helper code/advice} you could {point to/give us}?
Thank you so much!
You got it.
If you want to avoid going back and forth, you can invoke the optional UHDM uniquification phase:
- In Surelog option -elabuhdm, or
- after reloading UHDM, invoke the UHDM elaborator in your main: (2 lines of code) https://github.com/alainmarcel/UHDM/blob/4926f83bfe5b8d7f16ffd9572e280e6236fca25c/util/uhdm-dump.cpp#L131)
That way you can navigate the uhdmTopModules and don't need to go to the uhdmAllModules. Memory is larger or course, but all types and sizes are uniquified.
Wow, neat! Thank you