chiggs

oc_jpegencode

Fork of OpenCores jpegencode with Cocotb testbench

UVM

Mirror of the Universal Verification Methodology from sourceforge

mdx_wavedrom

Python Markdown extension for inserting wavedrom waveform diagrams into markdown output

hidden_wires

Proof-of-concept: Use static variables inside SystemVerilog functions to communicate between modules

alt.hdl

Exploration of alternative hardware description languages

reduct

Reduce a toolchain to the bare minimum set of files required

cocotb

Coroutine Co-simulation Test Bench

home

Scripts and settings from my home area

iverilog

Icarus Verilog

support_tickets

Cut-down testcases for various EDA vendor support tickets

sv_benchmarking

Some random benchmarks of SV and Python

bing_bang_bong

Test

comp.lang.verilog

Code samples etc from alt.lang.verilog

freecellera.github.io

fusesoc

fusesoc_vunit_demo

Demo project for FuseSoC + VUnit integration

md5cracker

A Hardware MD5 Cracker for the Cyclone V SoC

nvc

VHDL compiler and simulator

oc_mkjpeg

Fork of the mkjpeg project from OpenCores

orconf

OpenRISC Conference Website

post-mortems

A collection of postmortems. Pull requests welcome!

testcode

simple test repo

theopencorps

TheOpenCorps website built on Google App Engine

travis_experiment

vunit

VUnit is a unit testing framework for VHDL