chenshih's starred repositories

verilator

Verilator open-source SystemVerilog simulator and lint system

Language:C++License:LGPL-3.0Stargazers:2334Issues:72Issues:3378

moderngpu

Patterns and behaviors for GPU computing

Language:C++License:NOASSERTIONStargazers:1608Issues:110Issues:34

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

Language:PythonLicense:BSD-2-ClauseStargazers:1144Issues:65Issues:386

pretrain-gnns

Strategies for Pre-training Graph Neural Networks

Language:PythonLicense:MITStargazers:948Issues:17Issues:63

pythontex

A LaTeX package that executes Python and other code in LaTeX documents, and includes the output

Xyce

The Xyce™ Parallel Electronic Simulator

Language:CLicense:GPL-3.0Stargazers:373Issues:26Issues:68

Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Language:BluespecLicense:Apache-2.0Stargazers:347Issues:22Issues:15

Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Language:VerilogLicense:Apache-2.0Stargazers:301Issues:24Issues:26

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Language:VerilogLicense:NOASSERTIONStargazers:287Issues:11Issues:344

mflowgen

mflowgen -- A Modular ASIC/FPGA Flow Generator

Language:PythonLicense:BSD-3-ClauseStargazers:214Issues:18Issues:33
Language:PythonLicense:BSD-3-ClauseStargazers:207Issues:16Issues:23

Toooba

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Language:VerilogLicense:NOASSERTIONStargazers:156Issues:15Issues:4

freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

Main

Main page

Language:Emacs LispLicense:MITStargazers:125Issues:14Issues:6

merge-spmm

Code for paper "Design Principles for Sparse Matrix Multiplication on the GPU" accepted to Euro-Par 2018

Language:C++License:Apache-2.0Stargazers:68Issues:29Issues:10

ICFP2020_Bluespec_Tutorial

Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference

Language:HTMLLicense:Apache-2.0Stargazers:61Issues:7Issues:2

practical-cplusplus-design

Source code for 'Practical C++ Design' by Adam B. Singer

Language:C++License:NOASSERTIONStargazers:57Issues:7Issues:0

BluespecIntroGuide

An introductory guide to Bluespec (BSV)

bdw

BSC Development Workstation (BDW)

Language:TclLicense:NOASSERTIONStargazers:27Issues:6Issues:2

modern-data-mining-algorithms-in-cpp-cuda-c

Source Code for 'Modern Data Mining Algorithms in C++ and CUDA C' by Timothy Masters

MasterRTL

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

AP-GCN

Adaptive Propagation Graph Convolutional Network

Language:Jupyter NotebookLicense:MITStargazers:22Issues:3Issues:4

DesignCNNAccelerators

Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017

FEATHER

A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

Language:VerilogStargazers:15Issues:0Issues:0
Language:Jupyter NotebookStargazers:11Issues:1Issues:0

planetoid_datasets

Planetoid datasets. Consist of Cora, Pubmed, Citeseer, Large_Cora, nell.0.1, nell.0.01, nell.0.001.

skywater-130nm

ASIC Design kit for Skywater 130 for use with mflowgen

Language:VerilogStargazers:8Issues:0Issues:2

tgopt

TGOpt: Redundancy-Aware Optimizations for Temporal Graph Attention Networks

Language:PythonLicense:MITStargazers:6Issues:2Issues:0

language-bh

TextMate-style grammar for syntax highlighting of Bluespec BH/Classic

Language:BluespecLicense:NOASSERTIONStargazers:2Issues:5Issues:5