chenshih1

modern-data-mining-algorithms-in-cpp-cuda-c

Source Code for 'Modern Data Mining Algorithms in C++ and CUDA C' by Timothy Masters

practical-cplusplus-design

Source code for 'Practical C++ Design' by Adam B. Singer

planetoid_datasets

Planetoid datasets. Consist of Cora, Pubmed, Citeseer, Large_Cora, nell.0.1, nell.0.01, nell.0.001.

Toooba

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

bdw

BSC Development Workstation (BDW)

DesignCNNAccelerators

Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017

ICFP2020_Bluespec_Tutorial

Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference

tgopt

TGOpt: Redundancy-Aware Optimizations for Temporal Graph Attention Networks

language-bh

TextMate-style grammar for syntax highlighting of Bluespec BH/Classic

BluespecIntroGuide

An introductory guide to Bluespec (BSV)

Main

Main page

FEATHER

A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

moderngpu

Patterns and behaviors for GPU computing

merge-spmm

Code for paper "Design Principles for Sparse Matrix Multiplication on the GPU" accepted to Euro-Par 2018

perfmon

GKAT

pythontex

A LaTeX package that executes Python and other code in LaTeX documents, and includes the output

skywater-130nm

ASIC Design kit for Skywater 130 for use with mflowgen

mflowgen

mflowgen -- A Modular ASIC/FPGA Flow Generator

asap7

freepdk-45nm

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

AP-GCN

Adaptive Propagation Graph Convolutional Network

Xyce

The Xyce™ Parallel Electronic Simulator

verilator

Verilator open-source SystemVerilog simulator and lint system

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

MasterRTL

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

pretrain-gnns

Strategies for Pre-training Graph Neural Networks