bluespec / Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

bluespec/Flute Issues

Questions about some errors when running simulation or tests
Updated 7 months ago2
Compressed hints should be legal
Updated a year ago1
make compile fail (CPU.bsv line 319)
Closed 2 years ago1
UART address unsupported while communicating between the flute core and uart ip through AXI4 bus
Closed 3 years ago3
Flute on GaloisInc/BESSPIN-GFE
Updated 3 years ago
Modify JTAG settings for different boards
Updated 3 years ago
Error while regenerating SSITH P2 verilog files
Closed 3 years ago11
RoundMode in ISA_Decls conflicts with that in FloatingPoint.bsv
Updated 3 years ago1
Near_Mem_TCM is missing
Updated 4 years ago
FPGA Synthesis
Closed 4 years ago
plic-test compile and sim fail
Updated 4 years ago
找不到顶层文件
Closed 4 years ago3
Where Can I get the Bluespec systemverilog compiler?
Closed 5 years ago1
Verification / Test Coverage
Updated 5 years ago
Include_RV32IMU.mk: No such file or directory
Closed 5 years ago1