Chang Meng's repositories
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
Language:CNOASSERTION000
BACS
Benchmarks for Approximate Circuit Synthesis
Language:Verilog000
changmg.github.io
Chang Meng's Homepage: https://changmg.github.io/
BLASYS
An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
Language:VerilogBSD-3-Clause000
Language:C++000
cryptominisat
An advanced SAT solver
Language:C++NOASSERTION000
evoapproxlib
Library of approximate arithmetic circuits
Language:VerilogMIT000
mockturtle
C++ logic network library
MIT000
sis
Logic Synthesis System from UC Berkeley (Unofficial Distribution)
NOASSERTION000