cfelton / minnesota

A collection of HDL cores written in MyHDL.

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Memory map builder

cfelton opened this issue · comments

Currently the memory-map register bus (CSR) follows the old-school scheme defining the data and address bus widths. This shouldn't be the case. Once the bus is defined it should decide the address space and data widths. High-level parameters can be provided to help steer the building, example max throughput and addressing type (one-hot, etc.).

The builder will then output a map and structures to automatically access.