Robert Balas's repositories
ddd
GNU DDD is a graphical front-end for command-line debuggers such as GDB, DBX, WDB, Ladebug, JDB, XDB, the Perl debugger, the bash debugger bashdb, the GNU Make debugger remake, or the Python debugger pydb. This is a git conversion of the original svn repository. Focus on RISC-V support.
better-google
Userscript to Better (or Older and Good) Google
brain2llvm
A small brainf*ck jit and interpreter
cascade
A Just-In-Time Compiler for Verilog from VMware Research
core-v-freertos
FreeRTOS for the CORE-V-MCU
counsel-projectile
Ivy UI for Projectile
dummy_vip
Files for the IP Integration Exercise
elf_diff
A tool to compare ELF binaries
gentoo
The Gentoo ebuild repository mirror
riscv
RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU
riscv-dejagnu
riscv-dejangu with PULP specific patches
riscv-disassembler
Single file RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
riscv-glibc
riscv-glibc with PULP specific patches
riscv-plic-spec
PLIC Specification
spike-instruction-trace-patch
Patch file for RISCV's spike to generate csv test vectors to aid the verification of Instruction trace encoder implementation
swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
trace_debugger
Capture retired instructions of a RISC-V Core and compress them into a sequence of packets.
trdb
RISC-V processor tracing tools and library
vcddiff
Basic VCD comparison tool, for Verilator testing
verilog-axi
Verilog AXI components for FPGA implementation
verilog-axis
Verilog AXI stream components for FPGA implementation
verilog-parser
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
zForth
zForth: tiny, embeddable, flexible, compact Forth scripting language for embedded systems
zipcpu
A small, light weight, RISC CPU soft core