Bluespec, Inc.

Bluespec, Inc.'s repositories

Flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

Language:BluespecApache-2.0345 22 15

Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Language:VerilogApache-2.0299 24 26

Toooba

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

Language:VerilogNOASSERTION150 15 4

RISCV_gdbstub

A gdbstub for connecting GDB to a RISC-V Debug Module

Language:CApache-2.021 8 1

Accel_AES

Language:VerilogApache-2.016 80

AWSteria_Infra

"Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)

Language:VHDL14 7 3

riscv-openocd

Language:CGPL-2.07 30

RISCV_Debug_Module

Language:BluespecApache-2.06 70

riscv-tools

Language:Shell5 40

AHB-Lite

AHB-Lite adapters, initiators and targets.

Language:Bluespec2 60

mcu-release

A release repository for the mcu class of CPUs

Language:Bluespec2 6 5

APB

Language:Bluespec1 50

brvf-tools

A collection of tools used by various RISC-V projects

Language:Python1 60

Near_Mem

All the different flavours of near-mem modules may eventually reside here.

Language:Bluespec1 60

AWS_Generic_Getting_Started

Language:Python000

CLINT

Timer and SW interrupts module

Language:Bluespec050

mcu-core

The source files comprising the MCU core

Language:Bluespec050

PLIC

Platform Level Interrupt Controller

Language:Bluespec050

riscv-tools-feedstock

Language:ShellBSD-3-Clause010

Tiny_TCM

A resource constrained TCM implementation.

Language:Bluespec050