A program to simulate L1 cache misses to a 3 level Cache hierarchy for various applications. The simulator is programmed for three different cache inclusion policies, i.e inclusive, exclusive, non-inclusive-non-exclusive (NINE).
The cache-simulator is developed as a part of the Assignment-1 for the course Advanced Computer Architecture (CS622A), Fall Semester - 2019, instructed by Prof. Mainak Chaudhury.
The results of the simulation are compiled here. And the project report can be found here.
| Name | Roll | |
|---|---|---|
| Aditya Rohan | raditya@iitk.ac.in | 160053 |
| Aniket Pandey | aniketp@iitk.ac.in | 160113 |
Make sure that the L1 miss-traces are present in a directory named
traces in the root folder of the project.
Part 1: Set associative L2/L3 cache with LRU eviction policy.
> make process # Process miss traces in a relevant format> make simulate # Build and run the simulator on the processed tracesNote: Do make part1 to run the above two make commands together.
Total execution time is about 2.5 Minutes.
Part 2: Fully associative L3 cache with LRU/Belady's MIN eviction policy.
> make fa-lru # Model FA-L3 cache with LRU Inclusion policy> make fa-min # Model FA-L3 cache with Belady's MIN Inclusion policyNote: Do make part2 to run the above two make commands together.
Since the Belady's optimal replacement policy looks into the future to figure out which block to replace, running it with 10+ million trace entries can take huge amount of time. For instance, sphinx3, which performs terribly with even the best cache organization, can easily take more than 8 hours to complete under Belady's MIN policy.