andreaskurth

memora-rs

Memora: Build Artifact Cache for Git Repositories

docker-rust-centos

Docker Image for Rust on CentOS

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

BF-FFT-Demo

Graphical demo application for the FFT algorithm on an ADSP-BF532

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

docker-rust-ubuntu

Docker Image for Rust on Ubuntu

gh-workflow-test

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

ibex-demo-system

A demo system for Ibex including debug support and some peripherals

lowrisc-fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

moore

HDL compiler based on LLHD

morty

A SystemVerilog source file pickler.

noxim

Network on Chip Simulator

opentitan

OpenTitan: Open source silicon root of trust

ot-sca

Side-channel analysis setup for OpenTitan

pspin

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

pulp-configs

Contains JSON description of pulp configurations

pulp-rt

pulp-sdk

pulp-tools

riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

slm_conv

Convert loader files to SLM files for RTL simulation

SpinalHDL

SpinalHDL core

two-tree-demo