alexzhang007

Reorder-buffer-4-way-O3-CPU-verilog

ReOrder buffer implementation for superscalar out of order CPU

CnC_Remastered_Collection

lizard

Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL

ConvNetAsic

rv8

RISC-V simulator for x86-64

MIPS-CPU-Simulator

This is a mips simulator I wrote once to help my understanding of pipelines, branch prediction, assembly language, and more.

miaow

An open source GPU based off of the AMD Southern Islands ISA.

gpgpu-sim_distribution

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

attila-sim

iverilog

Icarus Verilog

Cache

Verilog Cache-4Ways IP development

MipsCpu

A six pipelined (Fetch, Decode, Issue, Execute, Memory, WriteBack) cpu that only implements parts of mips instructions in Verilog

FloatPointArithmetic

Float Point Add, Multiply and Division.

haroopad

Haroopad - The Next Document processor based on Markdown