Alex Zhang's repositories
FloatPointArithmetic
Float Point Add, Multiply and Division.
wishbone_uvc
Wishbone protocol open source universal verification component (UVC). It is easy to be used in UVM verification environment for opencpu.
Arduino
open-source electronics prototyping platform
ariane
Ariane is a 6-stage RISC-V CPU
awesome-courses
:books: List of awesome university courses for learning Computer Science!
BrookGPU
The original Stanford Code befor becomming Brook Plus - pulled from Subversion 1889
Cores-SweRV
SweRV EH1 core
darknet
Convolutional Neural Networks
DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
e200_opensource
The Ultra-Low Power RISC Core
lizard
Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
MCGSim
Linux version of the simulation where it provide the MS solution in http://cs.lth.se/eda075/lectures/
minerva
A 32-bit RISC-V soft processor
MipsSimulator
Mips CPU binary code simulator with C++ code in cycle model
ModelFactory
A Matlab/Octave toolbox to create human body models
OpenCNN
Open Convolution Core
OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
Parser-Verilog
A Standalone Structural Verilog Parser
RiscGpu
RISC GPU
riscv-isa-sim
Spike, a RISC-V ISA Simulator
sha3
FIPS 202 compliant SHA-3 core in Verilog
SoC-Design-DDR3-Controller
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
tensorflow
An Open Source Machine Learning Framework for Everyone
Verilog-Quadrature-Decoder-I2C-Slave
Verilog Quadrature Decoder with I2C slave to retrieve counts and reset counters
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
vscale
Verilog version of Z-scale (deprecated)