Alexey's starred repositories

click

Python composable command line interface toolkit

Language:PythonLicense:BSD-3-ClauseStargazers:15553Issues:187Issues:1566

ratatui

Rust library that's all about cooking up terminal user interfaces (TUIs) 👨‍🍳🐀

Language:RustLicense:MITStargazers:9427Issues:32Issues:310

clients

Bitwarden client apps (web, browser extension, desktop, and cli).

Language:TypeScriptLicense:NOASSERTIONStargazers:9033Issues:125Issues:3983

sha256-animation

Animation of the SHA-256 hash function in your terminal.

Language:RubyLicense:MITStargazers:3324Issues:35Issues:2

CppDeveloperRoadmap

The roadmap for learning the C++ programming language for beginners and experienced devs.

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Language:C++License:NOASSERTIONStargazers:1327Issues:49Issues:950

ubbook

Путеводитель C++ программиста по неопределенному поведению

lady-deirdre

Compiler front-end foundation technology.

OSVVM

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Language:VHDLLicense:NOASSERTIONStargazers:221Issues:27Issues:66

open5G_phy

A ressource efficient, customizable, synthesizable 5G NR lower PHY written in Verilog

Language:Jupyter NotebookLicense:AGPL-3.0Stargazers:186Issues:12Issues:15

vhdl-extras

Flexible VHDL library

corsair

Control and Status Register map generator for HDL projects

Language:PythonLicense:MITStargazers:96Issues:12Issues:32

FEC

FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)

Language:SystemVerilogLicense:MITStargazers:84Issues:13Issues:3

InverviewQuestions

Коллекция вопросов, которые мне задавали на собеседованиях (вакансия программист-разработчик C++)

Language:C++License:GPL-3.0Stargazers:64Issues:3Issues:2

Podcasts

нерегулярный подкаст о жизни ресечеров по обе стороны океана

rtcclock

A Real Time Clock core for FPGA's

Language:VerilogStargazers:22Issues:5Issues:0

uvm_sin_cos_table

Contains source code for sin/cos table verification using UVM

Language:SystemVerilogStargazers:20Issues:4Issues:0

uvm_modem

UVM components for DSP tasks (MODulation/DEModulation)

Language:SystemVerilogLicense:GPL-3.0Stargazers:14Issues:1Issues:0

.settings

Setup configuration used in my videos

Language:LuaLicense:MITStargazers:12Issues:0Issues:0

complexpack

complexpack is a complex arithmetic package written in VHDL.

Language:VHDLLicense:NOASSERTIONStargazers:7Issues:2Issues:0

make-fpga

Set of scripts for Vivado's project handling

Language:TclLicense:MITStargazers:7Issues:1Issues:11