esynr3z / corsair

Control and Status Register map generator for HDL projects

https://corsair.readthedocs.io

esynr3z/corsair Issues

Verilog waccess not aligned with output data
Updated 3 months ago
Verilog build failed when using multistring description #bug
Updated 3 months ago
c-headers: struct and bit field layout are implementation defined...
Updated a year ago
feature request: support symbolic constants for `base_address`, (do not require it to be a number)
Updated a year ago1
Constants and expressions support
Updated a year ago
Addressing mode support
Updated a year ago
Enumeration types support
Updated a year ago
Interrupt support
Updated a year ago
#enhancement: wavedrom bitfield adding `lanes` to csrconfig
Updated a year ago2
AXI BResp and RResp
Updated a year ago5
base_address for RTL modules
Closed a year ago2
bugs in c header generation
Closed a year ago3
Access mode 'rolh' can miss a latch
Closed a year ago2
#enhancement: add informative header to all auto-generated files
Updated a year ago
Memory interface support
Updated a year ago
Acess mode 'roc' can miss a latch
Updated a year ago
VHDL target: compare parametric address to constants
Closed a year ago1
Verilog AXI read queue for first word fall through fifo.
Closed a year ago2
Queue read not working when FIFO is ready in advance
Closed a year ago2
Resolve timescale issues
Closed 2 years ago
A write-only register with Hardware 'access' option, uses a undeclared *_rdaccess signal
Closed 2 years ago1
Confusing terminology: MSB & LSB vs Offset & Width
Updated 2 years ago
Minor bug in VHDL file generation (csr_*_ren signal)
Closed 2 years ago7
CMSIS SVD
Updated 2 years ago2
#enhancement: add gitignore which included all auto-generated files
Updated 2 years ago
Optional timeout on reads and writes
Updated 2 years ago
Move access and hardware from bitfields to reg
Closed 2 years ago2