ahmed-alllam / AlphaLogos

Boolean Function Analyzer and Synthesis Optimization Tool

Home Page:http://alpha-logos-1464863388.eu-west-3.elb.amazonaws.com/

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AlphaLogos!

AlphaLogos: Logic Synthesis Optimization

View Demo · Report Bug · Request Feature

About The Project

AlphaLogos is a logic synthesis optimization tool that takes a logic circuit and optimizes it using the Quinn-McCluskey algorithm. It is designed with the intention to aid individuals in understanding and visualizing the process of logic minimization, which is crucial in digital design. The application leverages the power of the Quine-McCluskey algorithm to simplify logical expressions, rendering a more comprehensible and optimized version of the input logic circuit. The core functionalities include generating truth tables, obtaining minimized Boolean expressions, and visualizing the corresponding Karnaugh Maps and logic circuits. You can access the project demo using this link.

You can delve deeper into the developmental journey and the technical aspects of AlphaLogos by exploring the Project Report, which is available here. For a closer look at the various test cases and their outcomes, feel free to check out the Test Cases Report here.

Features

  1. Generate Truth Table: Create a truth table based on the given logical expression.
  2. Obtain Canonical SoP and PoS: Acquire the canonical Sum of Products (SoP) and Product of Sums (PoS) forms of the logical expression.
  3. Get Prime Implicants (PIs): Identify the prime implicants derived from the logical expression.
  4. Get Essential Prime Implicants (EPIs): Determine the essential prime implicants which are crucial for the minimized expression.
  5. Get Uncovered Minterms by EPIs: Identify the minterms that are not covered by the essential prime implicants.
  6. Minimize the Expression: Utilize the Quine-McCluskey algorithm to minimize the logical expression.
  7. Get Minimum Number of MOSFET Transistors: Calculate the minimum number of MOSFET transistors required for the circuit.
  8. Draw Karnaugh Map: Visualize the logic minimization process through a Karnaugh Map.
  9. Draw Digital Circuit Simulation: Generate a digital circuit simulation based on the minimized expression for a hands-on understanding and visualization

Tech Stack

The project utilizes the following technologies and libraries:

  • C++
  • AWS
  • Docker
  • Crow
  • JavaScript
  • Boost
  • Jinja2
  • CMake
  • Catch2
  • LaTeX
  • Yosys

Screenshots

Building and Running the Project

To build and run the AlphaLogos project using Docker, follow the steps below:

  1. Clone the Repository:

    git clone https://github.com/ahmed-alllam/alphalogos.git
    cd alphalogos
  2. Build the Docker Image:

    docker build -t alphalogos:latest .
  3. Run the Docker Container:

    docker run -p 8000:8000 alphalogos
  4. Access the Application: After executing the commands above, open your browser and navigate to http://localhost:8000 to access the application.

Created By

Ahmed Allam - LinkedIn - ahmedeallam@aucegypt.edu - 900214493

Mohamed Mansour - Hamdy47@aucegypt.edu - 900222990

Mohamed Abdelmagid - LinkedIn - mabdelmagid@aucegypt.edu - 900223215

About

Boolean Function Analyzer and Synthesis Optimization Tool

http://alpha-logos-1464863388.eu-west-3.elb.amazonaws.com/

License:MIT License


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