Tsukasa OI (a4lg)

a4lg

Geek Repo

Location:Shiga Japan

Home Page:https://a4lg.com/

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Tsukasa OI's repositories

fast-tlsh

Fast TLSH-compatible Fuzzy Hashing Library in pure Rust

Language:RustLicense:Apache-2.0Stargazers:4Issues:0Issues:0

ffuzzy

Library to generate / parse / compare ssdeep Context Triggered Piecewise Hashes (CTPH)

Language:RustLicense:GPL-2.0Stargazers:3Issues:2Issues:0
Language:CLicense:GPL-2.0Stargazers:2Issues:0Issues:0

collect_slice

Collect an iterator into a slice.

License:MITStargazers:0Issues:0Issues:0
License:CC-BY-4.0Stargazers:0Issues:0Issues:0
License:GPL-2.0Stargazers:0Issues:2Issues:0

nugine-simd

SIMD-accelerated operations

License:MITStargazers:0Issues:0Issues:0
License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-binutils-devmemo

binutils development memo (for RISC-V)

Language:PythonStargazers:0Issues:0Issues:0

riscv-c-api-doc

Documentation of the RISC-V C API

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-control-transfer-records

This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-crypto

RISC-V cryptography extensions standardisation work.

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

License:NOASSERTIONStargazers:0Issues:0Issues:0

riscv-indirect-csr-access

Smcsrind/Sscsrind is an ISA extension that extends the indirect CSR access mechanism originally defined as part of the Smaia/Ssaia extensions, in order to make it available for use by other extensions without creating an unnecessary dependence on Smaia/Ssaia.

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-isa-manual

RISC-V Instruction Set Manual

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riscv-isa-sim

Spike, a RISC-V ISA Simulator

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riscv-opcodes

RISC-V Opcodes

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riscv-profiles

RISC-V Architecture Profiles

Language:MakefileLicense:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-rvm-csi

RVM-CSI (RISC-V eMbedded - Common Software Interface) aims to provide a source-level portability layer providing a simplified transition path between different microcontrollers based on RISC-V. This repo contains the specification documentation, and language-specific source files for implementing the API (initially, C header files).

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-sbi-doc

Documentation for the RISC-V Supervisor Binary Interface

Language:MakefileLicense:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-smcdeleg-ssccfg

Supervisor Counter Delegation Architecture Extension

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-smcntrpmf

Cycle & Instret Privilege Mode Filtering Architecture Extension

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-smmtt

This specification will define the Smmtt privilege ISA extensions required to support the supervisor domain isolation for many isolation use cases e.g. confidential-computing, fault isolation and so on.

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.

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riscv-zacas

riscv-zacas created from docs-spec-template template

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

tg-nexus-trace

RISC-V Nexus Trace TG documentation and reference code

License:CC-BY-4.0Stargazers:0Issues:0Issues:0

thead-extension-spec

T-head vendor extension Instruction Set spec

License:Apache-2.0Stargazers:0Issues:0Issues:0
License:NOASSERTIONStargazers:0Issues:0Issues:0