ZPNMiaoHeng

aider

aider is AI pair programming in your terminal

neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

tmux

tmux source code

alacritty

A cross-platform, OpenGL terminal emulator.

ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

nvim

The Ultimate NeoVim Config for Colemak Users

coc.nvim

Nodejs extension host for vim & neovim, load extensions like VSCode and host language servers.

llm.c

LLM training in simple, raw C/CUDA

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

reference

为开发人员分享快速参考备忘清单(速查表)

abstract-machine

A minimal, modularized, and machine-independent hardware abstraction layer

iEDA

yosys-sta

grok-1

Grok open release

Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

riscv-chisel-book

zsh4humans

A turnkey configuration for Zsh

advanced-computer-architecture

体系结构研讨 + ysyx高阶大纲 (WIP

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

biriscv

32-bit Superscalar RISC-V CPU

riscv

RISC-V CPU Core (RV32IM)

NutShell

RISC-V SoC designed by students in UCAS

CPP

Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.

CPP

Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

gem5

The official repository for the gem5 computer-system architecture simulator.

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

XiangShan

Open-source high-performance RISC-V processor

rCore-Tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.