ZPNMiaoHeng

lazy_nvim

ysyx-workbench

drawioFolder

llm.c

LLM training in simple, raw C/CUDA

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

OSCPU

yosys-sta

aes

am-kernels-6

gem5

rocket-chip

Rocket Chip Generator

NutShell

RISC-V SoC designed by students in UCAS

chipyard

neorv32

neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

CPP

Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.

e203_qust

rt-thread

RT-Thread is an open source IoT real-time operating system (RTOS).

iEDA-data-set

SparrowRV

tinyriscv

tinyriscv_v

riscvmini

opene902

rCore-Tutorial-v3

Let's write an OS which can run on RISC-V in Rust from scratch!

e203

Study

Hash

yxyx_ZPN

It is use to study

am-kernels