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Xeenog's starred repositories

tx-line-calculator

A transmission line calculator for RF/microwave engineers

Language:JavaGPL-3.0600

neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Language:VerilogBSD-3-Clause4700

serv

SERV - The SErial RISC-V CPU

Language:VerilogISC133500

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language:PythonApache-2.0126600

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

80800

Python-Digital-Signal-Processing-Basics

📶 Python Scripts for the basics of Digital Signal Processing (DSP). Updating on a regular basis.

Language:Jupyter Notebook2100

Python-for-Signal-Processing

Notebooks for "Python for Signal Processing" book

Language:Jupyter NotebookNOASSERTION164600

Industrial-automation

Digital notes of Industrial Automation course

MIT400

TodoList

A todoList program written in C language.

Language:CGPL-3.0100

19doc

19 dokümanları

1600

paul-graham-turkce

Bu repo paulgraham.com adresindeki denemelerin Turkceye cevrilmis hallerinin yayinladigi gonulluluk ile buyuyen bir kaynaktir.

GPL-2.028200

cracking-the-coding-interview

:books: C++ and Python solutions with automated tests for Cracking the Coding Interview 6th Edition.

Language:C++BSD-3-Clause61900

Arduino

Arduino IDE 1.x

Language:JavaNOASSERTION1408000

TheAlgorithms-Python

TheAlgorithms/Python

Language:PythonMIT279500

awesome-roadmaps

View roadmaps about developer roles to help you learn

CC0-1.0193200

developer-roadmap

Interactive roadmaps, guides and other educational content to help developers grow in their careers.

Language:TypeScriptNOASSERTION28358700