VeriDevOps

VeriDevOps's repositories

RQCODE

Java implementation of Requirement as Code concept. STIG requiremeents testing for Windows 10 platform

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CICD_ARQAN_RQCODE_Github_Actions

Security Requirement Analysis GitHub Action

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CompleteTest

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Earlytool

An implementation of the approach presented in https://arxiv.org/abs/2201.11628

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THOE

THreat Oracle Engine (documentation only)

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ARQAN.GuthubSecurityIssues

classification of github issues: security and others

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ARQAN.GuthubSecurityIssues.web-interface

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ARQAN_Paris

Security Requirement Analysis GitHub Action

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mmt-security

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NALABS

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SEAFOX

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CICD_ARQAN_RQCODE_GitLab

CICD_ARQAN_RQCODE_GitLab

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CICD_ARQAN_RQCODE_Jenkins

Portable and flexible Jenkinsfile to perform requirements tagging and STIGs and tests suggestion

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Infuzetool

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mmt-dpi

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mmt-operator

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mmt-probe

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mmt-rca

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ModelioOpenSource

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Napkin

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project-example

Project example setup with CI/CD for VeriDevOps

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PyLC

The initial version of the automated PLC to Python translation framework, PyLC with support of Function Block Diagram (FBD) language. The framework consists of 4 different Python scripts for importing a PLCopen XML file, parsing it, extracting the information regarding each POU/Block, Python code generation, and finally, translation validation.

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