SvrAdityaReddy / Inter_Device_Communication_Protocols

Verilog Codes of various Inter Device Communication Protocols

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Inter Device Communication Protocols

In this repository we will be looking at verilog codes of various Inter Device Communication protocols like Universal Asynchronous Receiver Transmitter (UART), Serial Peripheral Interface (SPI).

Universal Asynchronous Receiver Transmitter (UART)

Terminologies used in UART

  • Start bit:- It is the first bit of one byte UART transmission. It is used to indicate the receiver that data bits are going to arrive i.e it indicates that data line is leaving it's idle state. In general idle state is Logic HIGH and Start bit is Logic LOW.

  • Stop bit:- It is the last bit of one byte UART transmission. It has the same logic level idle state.

  • Baud rate:- It is the approximate rate at which data can be transmitted. Approximately the time period of one bit in a UART transmission is inverse of Baud rate.

Serial Peripheral Interface (SPI)

Here communication happens between master chip and slave chips. The important terminologies used in SPI are as follow.

Terminologies used in SPI

It is a "Full Duplex Communication Protocol"

  • SCK:- This is the clock generated by master and is made available to all the slaves connected to it.

  • MOSI:- This is the one bit data line which corresponds to "Master Output and Slave Input" i.e data is sent by the master over this data line to the slave.

  • MISO:- This is the one bit data line which corresponds to "Master Input and Slave Output" i.e data is sent from slave to master over this data line.

  • SS:- This is known as "Slave Select". In general, the number of slave lines are equal to number of slaves that a master controls. In general slave select lines are kept "LOGIC HIGH" to disable all the slaves. Whenever a master wants to send data to a slave that particular slave's slave select line is made "LOGIC LOW" to enable the slave to receive the data sent by the master.

There are various modes of transmission which depends on the datasheet of the particular component. They are as follow [5]

Mode Clock Polarity (CPOL) Clock Phase (CPHA) Output Edge Data Capture
SPI_MODE0 0 0 Falling Rising
SPI_MODE1 0 1 Rising Falling
SPI_MODE2 1 0 Rising Falling
SPI_MODE3 1 1 Falling Rising

References

[1] Back to Basics: The Universal Asynchronous Receiver/Transmitter (UART)
[2] Fun and Easy SPI - How the SPI Protocol Works
[3] Serial Communication
[4] Serial Peripheral Interface (SPI) from sparkfun
[5] SPI library
[6] Clock Phase and Polarity

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Verilog Codes of various Inter Device Communication Protocols


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Language:SystemVerilog 64.0%Language:Verilog 36.0%