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SpinalHDL
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SpinalHDL
Scala based HDL
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1540
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78
Issues:
664
Forks:
299
SpinalHDL/SpinalHDL Issues
Can't infer width of Payload
Updated
5 days ago
Comments count
4
When’ Requirement: Merging ‘setWhen’ and ‘clearWhen’ in Verilog Output
Updated
6 days ago
『Help』Component Interface Name Changes Result in SpinalHDL Generating Excessive Redundant Module.v Files.
Updated
6 days ago
Comments count
4
new condtion syntactic suga
Updated
7 days ago
Comments count
6
Register fields with AccessType ROV don't get names
Updated
8 days ago
Seed does not work at parallel test of spinal sim
Updated
10 days ago
Comments count
4
JTAG VPI Simulation gets blocked by IO
Closed
10 days ago
Comments count
2
Underscore in literals
Closed
16 days ago
Comments count
5
Linux: Spaces in path break formal verification
Closed
13 days ago
Comments count
7
`privateNamespace` changes BlackBox component name
Updated
13 days ago
Comments count
1
Slower on the intranet network
Updated
18 days ago
Comments count
9
Support for memories with read latency higher than 1
Updated
23 days ago
Comments count
18
Performance of PriorityMux
Closed
a month ago
Comments count
18
Unknown reason for hierarchy violation
Closed
a month ago
Comments count
4
Are there some bugs in clockDomain.waitSampling() API?
Updated
a month ago
Comments count
10
Is there a "DONT_TOUCH" attribute for Components in Spinal ?
Closed
a month ago
Comments count
2
Parallel test execution in SpinalSim?
Closed
a month ago
Comments count
5
SpinalSim: onSamplings can't work properly with clock from a blackbox
Updated
2 months ago
Comments count
8
Redundant Flow API Calls.
Closed
2 months ago
Comments count
4
Wishbone BusIf SEL usage
Closed
2 months ago
Comments count
1
Blackboxing RAM with one read and one readWrite port
Updated
2 months ago
Comments count
2
Could not load XSI simulation shared library
Closed
2 months ago
Comments count
1
Checking for unknown values in simulation
Closed
2 months ago
Comments count
1
Dump ports of `Mem` in FST waveforms?
Closed
2 months ago
Comments count
3
Qsysify and Axi4: incorrect _hw.tcl generation
Closed
2 months ago
Comments count
1
[question] Trying to understand simulator wait apis (newbie)
Closed
2 months ago
Comments count
3
SimMutex locked repeatly crashes the simulation
Closed
2 months ago
Comments count
5
`assignDontCare` on Bundle element inside Union does not work
Updated
2 months ago
Comments count
14
HDElkDiagram generated html could not be convert ed to image using wkhtmltoimage correctly
Closed
2 months ago
Comments count
1
`Union` elements cannot be accessed inside SpinalSim properly
Closed
2 months ago
Comments count
1
StateMachines inside Plugins that have multiple instances have naming clash
Closed
3 months ago
Comments count
2
FiberPlugin addPrePopTask
Closed
3 months ago
Comments count
5
NamedType returns null when called outside of a Component
Closed
3 months ago
Comments count
11
When to override `clone`?
Closed
3 months ago
Comments count
7
How to use Union in IO port
Closed
3 months ago
Comments count
1
Plugin deadlock in circular dependency on Handle
Updated
3 months ago
Comments count
5
StreamMux with streamed select no correct join
Closed
3 months ago
Comments count
9
AxiLite4SlaveFactory generates combinatorial paths from inputs to ready outputs
Closed
3 months ago
Comments count
5
ClockDomain for input/output ports?
Updated
3 months ago
Comments count
10
Signal naming oversights
Closed
3 months ago
Comments count
3
`onSamplings` error when use inside clockdomain
Closed
3 months ago
Error when create a new ClockDomain in simulation
Closed
3 months ago
Comments count
2
SystemVerilog Interface Support
Closed
3 months ago
Comments count
2
Formal verification: Verilog generated when using synchronous resets is not understood by SymbiYosys
Updated
3 months ago
Comments count
10
Set clock domain from blackbox
Closed
3 months ago
Comments count
2
question about mem initialization
Updated
3 months ago
Comments count
11
How to generate RTL with parameters?
Closed
3 months ago
Comments count
2
Formal verifiation: SymbiYosys of SpinalTemplateSbt fails with "RG_WIDTH > 1 is not support by async2sync, use clk2fflogic." when using async reset
Closed
3 months ago
WishboneSlaveFactory - doWrite is never called in pipelined mode
Updated
3 months ago
Comments count
3
StreamFragmentWidthAdapter.make missing earlylast argument
Updated
3 months ago
Comments count
2
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