Sat J. Patel's starred repositories
SystemC-tutorial
Brief SystemC getting started tutorial
Cpp-CacheSim
A multi-threaded Cache Simulator implemented in C++11
Cache_Mapping_Technique
Simulator for Direct, Associative, Set Associative Mapping Technique in Cache Allocation
Cache-Simulator
PKU computer organization and architecture memory hierarchy simulator LAB
computer-architecture-projects
Computer architecture related projects
LRU-Cache-Simulator
A C++ simulation application of an LRU cache with VARIABLE cache size, block size, and associativity on a ~650000 memory address dump.
Cache-Simulator
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
cache-simulator
A processor cache simulator for the MIPS architecture
RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
axi_cheatsheet
A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
MachineLearning-AI
This repository contains all the work that I regularly did and studied from Medium blogs, several research papers, and other Repos (related/unrelated to the research papers).
salvisumedh2396.github.io
Portfolio Page
Toast-RV32i
Pipelined RISC-V RV32I Core in Verilog
computer-architecture-and-systems-resources
A curated list of Computer Architecture and Systems resources
awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
awesome-hdl
Hardware Description Languages
wb_intercon
Wishbone interconnect utilities
UVM-Examples
UVM examples and projects
Huffman-Codeing-IC
Implemented 8-bit Huffman coding algorithm using SystemVerilog.
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
AI-Expert-Roadmap
Roadmap to becoming an Artificial Intelligence Expert in 2022