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Sacusa / MIPSIM

A suite of simulators for a limited subset of MIPS32 ISA.

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computer-architecturecycle-accurateisamips-simulatormips32timing-simulator

MIPSIM

This is a suite of simulators for a limited subset of the MIPS32 ISA. It includes:

  1. A cycle-accurate instruction level simulator
  2. A timing simulator

This project is derived from CMU 18-447's labs. The shells have been used as-is. The simulator cores have been created from scratch.

About

A suite of simulators for a limited subset of MIPS32 ISA.

computer-architecturecycle-accurateisamips-simulatormips32timing-simulator

License:GNU General Public License v3.0

Languages

Language:Assembly 48.9%Language:Logos 27.1%Language:C 22.8%Language:Batchfile 0.6%Language:Python 0.6%Language:Makefile 0.0%