SJTU-ECTL / SCGen

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SCGen: A Versatile Generator Framework for Agile Design of Stochastic Circuits

Requirements

  • OpenCV
  • GiNaC
  • Ninja
  • Other essential building tools (g++, cmake, etc)

Building

cmake -B build -G Ninja
cd build
ninja

File structure

  • Benchmarks includes some test circuits to evaluate the performance of SCGen
  • Circuits_API stores the cirucits used to evaluate the DSE acceleration methods. Circuits designed by users are also stored here. An example is in Circuits_API/circuit_api_example.cpp.
  • include stores the source code of SCGen.
  • Verilog stores some commonly used modules in the Verilog/Modules folder. The generated Verilog code will also go here. Note: in order to use the Verilog code generated by some circuits, users should copy some commonly used modules in Verilog/Modules to the generated folder.

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Languages

Language:C++ 99.0%Language:CMake 1.0%