Seyed Ruhallah Qasemi's starred repositories
particle_detector
Detector for alpha, beta and other particles
caravel_tia
High bandwidth TIA
Design-of-6T-CMOS-SRAM
This design is done as part of Cloud based analog IC design Hackathon conducted by IITH in collaboration with VSD and Synopsys
CMOS-32x8-SRAM
A 32x8 SRAM Memory including drivers, differential amps, and decoder
32-bit-SRAM-
32-bit SRAM implementation in eSim using Skywater 130nm CMOS technology
5-Stage-2.92-Ghz-CMOS-VCO
This is a documentation of the steps involved in designing a VCO on the SYNOPSYS Custom Compiler - 28nm PDK
20GHz-integer-N-PLL-in-65nm-CMOS-process
Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
Analog-Design-of-Bootstrapped-Switch
This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A comparison is done between several topologies, showing the ENOB, SNR, & SFDR achieved in each case.
Layout-Design-for-an-8-bit-Microprocessor
Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS VLSI technology on Tanner EDA toolchain.
Analog-Design-of-Asynchronous-SAR-ADC
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
Layout-Design-of-an-8x8-SRAM-array
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Digital-Calibration-of-SAR-ADC
Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)