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Roghnaigh's starred repositories

MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.

Language:VerilogMIT2300

MIPS CPU implemented in Verilog

Language:VerilogGPL-3.055000

5-stage pipelined 32-bit MIPS microprocessor in Verilog

Language:VerilogGPL-3.010600

A 5-stage pipelined mips32 processor

Language:Verilog900

CPU based on MIPS with 5-stage pipeline and cache, working with DDR2 memory and SD card.

Language:Coq3100

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

Language:VerilogLGPL-3.06900

Tiny MIPS for Terasic DE0

Language:Verilog3400

Mips处理器仿真设计

Language:Verilog1700

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

Language:Verilog18400