Beast code in Giters

Roghnaigh's repositories

A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.

Language:Verilog010

MIPS, Pipeline

Language:Verilog010

A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.

Language:VerilogLGPL-3.0010

MIPS CPU implemented in Verilog

Language:VerilogGPL-3.0010

An implementation of MIPS single cycle datapath in Verilog.

Language:Verilog010

Fully pipelined MIPS CPU in Verilog/SystemVerilog with advanced branch prediction, register renaming, and value prediction

Language:Verilog010